JPS62121573U - - Google Patents
Info
- Publication number
- JPS62121573U JPS62121573U JP784386U JP784386U JPS62121573U JP S62121573 U JPS62121573 U JP S62121573U JP 784386 U JP784386 U JP 784386U JP 784386 U JP784386 U JP 784386U JP S62121573 U JPS62121573 U JP S62121573U
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- conversion means
- current conversion
- sweep
- controlled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims 4
- 230000003111 delayed effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 230000003321 amplification Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
第１図は本考案による一実施例の回路図である
。第２図は従来の輝度制御回路図、第３図は第２
図の動作波形図である。
１，２，９：輝度制御用可変抵抗器、３，４，
１２，１５：抵抗器、５，５′：ＮＰＮトランジ
スタ、６，７：スイツチ回路、８：輝度増幅回路
、１０，１１：論理ゲート、１３，１４：ダイオ
ード、１６：コンデンサ。
FIG. 1 is a circuit diagram of an embodiment of the present invention. Figure 2 is a conventional brightness control circuit diagram, and Figure 3 is a diagram of a conventional brightness control circuit.
FIG. 3 is an operation waveform diagram of FIG. 1, 2, 9: Brightness control variable resistor, 3, 4,
12, 15: resistor, 5, 5': NPN transistor, 6, 7: switch circuit, 8: brightness amplification circuit, 10, 11: logic gate, 13, 14: diode, 16: capacitor.
Claims (1)
常掃引により２値制御される論理ゲートと遅延掃
引により２値制御される論理ゲートを有し、その
夫々の出力端子に電圧、電流変換手段を接続し、
前記遅延掃引により制御される論理ゲート出力側
の前記電圧、電流変換手段と並列に、直列接続さ
れたダイオードと電圧、電流変換手段を接続し前
記夫々の電圧、電流変換手段の他端にトランジス
タのベース接地回路のエミツタを接続し、ベース
に輝度電圧制御回路を結合し、コレクタを輝度制
御電流出力としたことを特徴とした輝度制御回路
。 An oscilloscope with a delayed sweep, which has a logic gate that is binary-controlled by normal sweep and a logic gate that is binary-controlled by delayed sweep, and a voltage and current conversion means is connected to the output terminals of each of the logic gates.
The voltage and current conversion means are connected in parallel with the voltage and current conversion means on the output side of the logic gate controlled by the delay sweep, and a transistor is connected to the other end of each of the voltage and current conversion means. A brightness control circuit characterized in that the emitter of a grounded base circuit is connected, a brightness voltage control circuit is coupled to the base, and the collector is used as a brightness control current output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP784386U JPS62121573U (en) | 1986-01-24 | 1986-01-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP784386U JPS62121573U (en) | 1986-01-24 | 1986-01-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62121573U true JPS62121573U (en) | 1987-08-01 |
Family
ID=30791674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP784386U Pending JPS62121573U (en) | 1986-01-24 | 1986-01-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62121573U (en) |
-
1986
- 1986-01-24 JP JP784386U patent/JPS62121573U/ja active Pending