JPS62118523A - Wiring formation - Google Patents

Abstract

PURPOSE:To make the intervals of wiring comprising polycrystalline silicon film and silicide films thereon narrower than the width of resist patterns by a method wherein a second insulating film masked by resist patterns is overetched by isotropic etching process. CONSTITUTION:An insulating film 4 such as SiO2, Si3N4 is formed on a polycrystalline silicon film 3 formed on a semiconductor 1 through the intermediary of another insulating film 2. Then resistpatterns 5 1mum L/S are formed on the film 4 using an exposure device with at least 1mum L/S performance. Next, insulating film patterns 4A smaller than the resist pattern 5 are formed by isotropic process using the resist pattern 5 as masks. When a metallic film 6 to be silicide is formed on overall surface; the parts on the polycrystalline silicon film 3 are changed into silicide films 7; residual metallic film 6 and the insulating films 4A are removed; and the polycrystalline silicon film 3 is etched using the silicide films 7 as masks, specified wiring patterns 8 can be formed.

Description

[Detailed Description of the Invention] [Summary] In order to make the wiring spacing between a polycrystalline silicon film and a silicide film thereon smaller than the resist pattern width, a layer thinner than the resist pattern width is formed on the polycrystalline silicon film. forming an insulating film, forming a metal film to become a silicide over the entire surface, making the portion on the polycrystalline silicon film a silicide film, removing the remaining metal film and insulating film;
The polycrystalline silicon film is etched using the silicide film as a mask.

[Conventional technology]

Semiconductor devices such as ICs and LSIs are becoming more and more highly integrated, and microfabrication technology for this purpose is also progressing2). In particular, fine patterning of wiring is an important process in the manufacturing process of semiconductor devices. Normally, wiring is processed into a wiring pattern by forming a conductive film and then selectively etching it using phosphorography technology.
Wiring pattern width and wiring spacing (accuracy) are determined depending on the performance of the exposure device (optical exposure device, X-ray exposure device, etc.) used to form the resist pattern.

[Problem that the invention seeks to solve]

An object of the present invention is to form a wiring pattern with a wiring interval smaller (thinner) than the minimum resist pattern width obtained by an exposure apparatus.

[Means for solving problems]

The above purpose is achieved by the following steps (a) to (c): (a) forming a polycrystalline silicon film on the first insulating film; (b) forming a second insulating film on the polycrystalline silicon film (1) Step of forming a resist pattern on the second insulating film; (1)
) Second insulation based on the resist pattern! Model is equal force 1-
1 Etching - culm; (e) Removing the resist pattern - 1 - culm; (force) forming a metal film on the entire surface to be silicided; Process of forming a silicide film; (ri) Second
A step of removing the metal film of the insulating film 1-; (G) a step of removing the second insulating film; and (21) a step of etching the polycrystalline silicon film using the silicide film as a mask. This is achieved by a method of forming interconnects consisting of a polycrystalline silicon film and a silicide film.

The polycrystalline silicon film constituting the wiring in the present invention is doped with impurities (phosphorus, boron, etc.) in order to provide conductivity (that is, lower the resistivity) (so-called doped polysilicon). However, as a wiring, it is a silicide I)), which has a resistivity of 11 (11), which is an order of magnitude higher than that of polycrystalline silicon. can.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in more detail by way of embodiments with reference to the accompanying drawings.

1A to 1F are partial cross-sectional views of a semiconductor device having wiring formed according to the wiring forming method according to the present invention.

A wiring pattern having narrow wiring intervals and consisting of a polycrystalline silicon film and a silicide film is formed in the following manner according to the present invention.

As shown in FIG. 1A, an insulating film 2 is formed on a semiconductor substrate 1 by a conventional method. For example, the SiO□ film 2 is formed by thermally oxidizing a silicon substrate 1tl. Polycrystalline silicon is deposited on this insulating film 2 by chemical vapor deposition (CVD) to form a polycrystalline silicon film 3 (for example, thickness:
200 nm). At this time, impurities (phosphorus, poron, etc.) are doped into the polycrystalline silicon film (for example, phosphorus concentration: about 1020 to 1021 pieces/crl).
. Sing is applied to this polycrystalline silicon film 3 by the CVD method.
Insulating film 4 such as 5iJn (for example, thickness: 101
00n is formed. Then, a resist is applied by the Svinko 1 method, exposed with a predetermined exposure device, and developed to form a 2-ζ resist pattern 5 on the insulating film 4. Exposure equipment that can form resist patterns with lines/spaces (■, /S) of 0.8 μm has also been developed, but in this case, a minimum of 1 μm 1. A resist pattern of 1 μrn L/S is formed using an exposure device with a performance of 1 μrn.

Next, as shown in FIG. 1B, an etching process is performed to isotropically etch the insulating film 4 using the resist pattern 5 as a mask to form an insulating film pattern 4A that is thinner than the resist pattern 5.

For example, SiO□ film 4 is IIF? Over-etching is performed with a solution to leave a SiO□ film pattern 4A with a width of 0.5 μm.

After the resist pattern 5 is removed using a solvent (or ashing), metals (Mo, W, etc.) react with silicon to become silicide, as shown in FIG. 1c.

Ti, Ta, Pt, etc.) by CVD or physical growth (P
A metal film 6 is formed by depositing the metal film 6 over the entire surface by CV) method. For example, a molybdenum (Mo) film 6 is formed with a thickness of 200 nm using a sputtering method.

Next, a heat treatment is performed to convert the metal film 6 of the polycrystalline silicon film 31 into a silicide 1 film 7 (FIG. 1D). At this time, the sixth metal film of the insulating film pattern 4A-1- remains as it is. In the case of M Oll'J, it reacts with silicone by heating at about 500 DEG C. for -2 minutes to form the Mo5iz film 7.

Thereafter, the metal film 6 remaining on the insulating film pattern 4A':z is removed using an appropriate etching agent, and the insulating film pattern 4A is further removed using an appropriate etching agent to form the polycrystalline silicon':I film 3. (Figure 1E). For example, by etching and notching the MO membrane 6 with aqua regia, 5 iOzl
Is the pattern 4A compatible with HF? Work and tweet at night.

Next, as shown in FIG. 1F, using the silicide film 7 as a mask, the exposed portion of the polycrystalline silicon film 3 is anisotropically etched by plasma etching or reactive ion etching (RIE). By this etching, the polycrystalline silicon film 3 is cut into a wiring pattern shape, and a predetermined wiring pattern 8 consisting of the polycrystalline silicon film 3 and its silicide film 7 is obtained. In this case, the wiring gap (S) of the wiring pattern is the convergence of the insulating film pattern 4A,
The distance is 0.5 pm, which is half the exposure device performance (1 μrn). Note that the wiring pattern width (ff) is 1.
The thickness is 5 μm. As for wiring, the larger the width, the smaller the resistance value, so if the distance between adjacent wiring is small and the total value of lines and spaces is the same as before, 1.1 is problematic, 1 is not. I actually prefer U7.

〔Effect of the invention〕

In the formation method according to the present invention, the wiring spacing (
(space) can be made smaller (about half) than the minimum line, length and space dimensions of the exposure device. Due to the current limitations of polylithography (although L, /S remain the same), the following melilithography 1-/, L is used especially for the formation of Δl wiring. A1 wiring is Mos+, ST is 2
It is now formed with a diameter of 111 μm or less. The problems that arise in this case are electromigration and disconnection. The present invention provides a solution to this problem. That is, even with the same degree of integration, thicker wiring can be formed.

[Brief explanation of drawings]

FIGS. 1A to 1F are partial cross-sectional views of a semiconductor device for explaining the steps of the wiring forming method according to the present invention. ■... Semiconductor substrate, 2... Insulating film, 3... Polycrystalline silicon film, 4... Insulating film, 4A... Insulating film pattern, 5... Resist pattern, 6... Metal Film, 7... Silicide film. Figure 1A Figure 1C, 4--Tsuka. Eyu. Figure 1

Claims (1)

[Claims] 1. The following steps (a) to (c): (a) forming a polycrystalline silicon film on the first insulating film; (b) forming a second insulating film on the polycrystalline silicon film; (c) forming a resist pattern on the second insulating film; (d) isotropically etching the second insulating film using the resist pattern as a mask; (e) etching the resist pattern on the second insulating film; Step of removing; (f) Step of forming a metal film to be silicided on the entire surface; (g) Step of turning the metal film on the polycrystalline silicon film into a silicide film by heat treatment; (h) Said second insulating film (i) removing the second insulating film; and (g) etching the polycrystalline silicon film using the silicide film as a mask. A method for forming wiring made of a polycrystalline silicon film and a silicide film thereon.