JPS62117369A - Hetero junction bi-polar transistor - Google Patents

Abstract

PURPOSE:To simultaneously reduce base and collector (emitter) serial resistances and improve characteristics by placing the base electrode between the other two electrodes, and providing electrodes in the collector or emitter layer which were buried in a semiconductor substrate through a buried layer which was selectively provided. CONSTITUTION:Natural GaAs 2 is epitaxially formed on a semi-insulating GaAs 1, and Si ions are implanted to form a collector and rising portion 3. Si is added, an N-GaAs collector layer 4 is provided, Be ions are implanted, and a collector region 4A is defined with a P<+> layer 5. A Be-added P<+>-GaAs base 6 and an N-AlxGa1-xAs emitter 7 are overlayed thereon. The Al composition ratio (x) increases from 0 to 0.3 between 10-100mm from the interface of a layer 6 and returns again to 0 at the surface, and it is near to an N<+> layer at the surface. After heat-treatment and activation of the impurities, an emitter region 7A is defined, an emitter electrode 8 of AuGe/Au, a collector electrode 10 and a Cr/Au base electrode 9 are provided. With this structure, the respective serial resistances of the base and collectors are simultaneously decreased, and the gate delay time or the cut-off frequency are improved.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a heterojunction bipolar transistor in which a base electrode is interposed between two other electrodes and is selectively provided in a collector or emitter region buried in a semiconductor substrate. By connecting the electrodes through the buried region, the base and collector (emitter) series resistances are reduced at the same time, improving characteristics such as gate delay time and cut-off frequency.

[Industrial application field]

The present invention relates to a heterojunction bipolar transistor,
In particular, it relates to improvements that allow simultaneous reduction of base and collector (emitter) series resistance.

Various compound semiconductor devices having heterojunctions such as gallium arsenide (Ga^s)/aluminium gallium arsenide (^IGaAs) have been developed, but heterojunction bipolar transistors are expected to be high-speed devices with large current drive capability, and There is a strong desire to put this into practical use as soon as possible.

[Conventional technology]

In a heterojunction bipolar transistor, at least the emitter region is made of a semiconductor whose forbidden band width is larger than that of the base region, and this has the effect of increasing the current injection efficiency between the emitter and base. Figure 4+a shows a schematic side sectional view of a conventional example in which the base-collector capacitance is reduced by forming the
1 and (b).

In the figure, 21 is a semi-insulating GaAs substrate, 23 is an n
++GaAs sub-collector region, 24 is n-type GaAs collector region, 25 is p+-type region 26 is p++GaAs
Base layer, 27 to n-type lGaAs emitter region, 28
29 is an emitter electrode, and 29 is a base electrode.

In the conventional example shown in (a) of the same figure, molecular beam epitaxial growth (M
BP, ) In the device, ■ Selective ion implantation (ion beam in acid) to form a di-type GaAs sub-collector region 23 in the semi-insulating GaAs substrate 21 or non-doped GaAs buffer layer; Area 2
4, ■ I) selective ion implantation to form the l-type region 25 and define the XI director region 24, ■ 1GIIA to the p + type GaAs base layer 2G and the n-type
The growth of a semiconductor layer to form the third emitter region 27 was performed 111 times to obtain the required semiconductor substrate.

In addition, in the conventional example of the same figure (bl), (1) n++GaAs
Selective ion implantation is performed successively to form the sub:2 director region 23 and the n-type GaAs:I director region 24, and
A p1 type GaAs base layer 26 and a semiconductor layer to be an n type GaAs emitter region 27 are grown.

In these semiconductor substrates, an emitter electrode 28 and a base electrode 2 are formed such that a 4;t: riF-type GaAs substrate 4;
9 and the collector electrode 30 are arranged as shown in the plan view illustrated in FIG.

[Problem that the invention attempts to solve]

In a conventional heterojunction bipolar transistor in which each electrode is arranged as described above, the interests of the base series resistance and the collector series resistance conflict with each other, and a compromise must be made by comparing the two at the time of design.

In other words, in order to reduce the base series resistance, the length of the emitter region 27 in the direction sandwiched between the base electrodes 29 is shortened (-, ) in FIG. However, as a result, the average distance between the emitter electrode 28 and the collector electrode 30 increases, leading to an increase in collector series resistance.

Therefore, there is a need for a structure that can address this dilemma and simultaneously reduce base series resistance and collector series resistance.

[Means for solving problems]

The problem is that a second semiconductor region of the first conductivity type, a third semiconductor region of the second conductivity type, and a first semiconductor region of the first conductivity type are selectively provided on the first semiconductor region of the first conductivity type. and a fourth conductive type semiconductor region are sequentially stacked, the third semiconductor region is a base region, one of the second and fourth semiconductor regions is a collector region, and the other is an emitter region. a first electrode connected to the semiconductor region of No. 4;
A base electrode connected to the third semiconductor region is interposed between the third electrode connected to the second semiconductor region C and the third electrode connected to the second semiconductor region via the semiconductor region The solution is a junction bipolar transistor.

[For production]

According to the present invention, as illustrated in FIG. 1, for example, when the collector is placed on the semiconductor substrate side, the base electrode 9, usually a part thereof, is arranged between the emitter electrode 8 and the collector electrode 10. , the connection of the two-I collector electrode 10 to the collector region is made by a sub-collector region selectively buried within the semiconductor substrate.

With this configuration, the shape of the emitter region 7^ is changed to the shape of the collector electrode I.
By making it shorter in the O direction and naturally narrowing the interval between each electrode, it is possible to simultaneously reduce the base series resistance and the ':I-rector series resistance.

〔Example〕

The present invention will be specifically explained below using examples.

FIGS. 2(a) to 2(d+) are schematic side sectional views in the order of steps showing the first embodiment of the present invention.

See Figure 2(a) 2 MB on semi-insulating GaAs substrate l
A non-doped GaAs buffer layer 2 is epitaxially grown to a thickness of, for example, about 1 μm using the E method.
If necessary, the position of silicon (Si':1) is moved to form the horizontal part of the sub-collector 9r1 region 3 by selective implantation using a focused ion beam.
Ion is 5×10I4 with energy of about -200keν
Inject about 10I4. If the thickness is to be further increased, this growth-implantation process is repeated, and then the rising portion of the sub-collector region 3 is formed in a similar process.

Figure 2 (see ill: For example, St is lXl0”~1×
An n-type GaAs collector layer 4 having a tope of about 10<17 >cm<-3> and a thickness of about 500 nm is epitaxially grown.

Next, in order to form the p+ type region 5 that defines the collector region 4A, for example, beryllium (Re) ions are implanted with an energy of -200 keν by the selective implantation method.
Xl01'cm-2 culm juice.

See Figure 2 (C): For example, beryllium (Be) is 1 x 1011' to 1 x 10190 I1 by the old Mi method.
P+ type G doped to about 1-1 and about 100nnn thick
rShinhachi base layer 6 and, for example, 1 with a thickness of 300 nm and a culm
A type 1 AIXG-XAS emitter layer 7 is grown.

However, the AI composition ratio X of the n-type AlxGa+XAs emitter layer 7 is from 10 to 100 from the interface with the base layer 6.
gradually increases from X = −O to 0.3 in the nm range 7
, near the L-surface, it becomes X-O again, and the impurity concentration is 1
The concentration is about ×10+7 to 1×10111clIl-3, but the concentration is set to be close to 1, 10I901n-3 near the surface.

Figure 2 (see di: This semiconductor Jk body is taken out of the M-meter device and subjected to heat treatment at a temperature of, for example, 700°C for about 1 hour to make the ion-implanted impurities active FI. Then, etching treatment is performed. defining an emitter region 7A;
The electrode formation region of the sub-collector region 3 is exposed.

The emitter electrode 8 and the collector electrode IO are arranged using, for example, gold germanium/gold (AuGe/Au), and the base electrode 9 is arranged using, for example, chromium/gold (Cr/^D). The example transistor element is completed.

FIG. 3 is a schematic side sectional view showing a second embodiment of the present invention, and the same reference numerals as in FIG. 2 indicate parts corresponding to the embodiment.

In this embodiment, the collector electrode 4A is made of non-doped GaA.
The s-buffer layer 2 is formed by the selective ion implantation method described above. In this ion implantation, for example, Si" is implanted at an energy of about -200 keV and a depth of about 3.times.10@13 cm.sup.-".

In the first embodiment, the collector electrode I of the emitter region 7^
The length of the emitter region in the collector electrode direction is 3 pTn, and the length of the emitter region in the direction perpendicular to this is 4 pTn.
Maximum oscillation frequency fmm with respect to the comparison sample with μm
Comparing
Improvements were achieved, demonstrating the effectiveness of the present invention.

In addition, in the above explanation ′:! Although the emitter is on the semiconductor substrate side, the same effect can be obtained in the case of a so-called inverted structure where the emitter is on the semiconductor substrate side.
It is clear that similar effects can be obtained not only in GaAs-based but also in heterojunction bipolar transistors using other semiconductors (Al).

〔Effect of the invention〕

As described above-1-, according to the present invention, the base series resistance and the ::11/ctor series resistance of a heterojunction bipolar transistor are simultaneously reduced, and the characteristics such as C, gate delay time, cutoff frequency, etc. are improved. , we will greatly contribute to the promotion of its practical application.

[Brief explanation of drawings]

FIG. 1 is a plan view showing one example of a heteri':] junction bipolar transistor according to the present invention, FIG. 2 is a schematic side sectional view in -r culm order of the first practical h1<- example of the present invention, and FIG. 3 4 is a schematic side sectional view of the second embodiment of the present invention, FIG. 4 is a schematic side sectional view of the conventional example, and FIG. 5 is a plan view of the conventional example. In the figure, 1 is a semi-insulating GaAs substrate, 2 is a non-doped GaAs buffer layer, and 3 is a type 1 GaAs substrate.
s sub-collector region, 4 is n-type GaAs collector layer, 4^ is collector region, 5 is p4-type region, 6 is p+-type GaAs base layer, 7 is n-type 1. GaAs emitter layer, 7^ is an emitter region, 8 is an emitter electrode, 9 is a base electrode, and 10 is a collector electrode. σE i), \toi), conventional, itching, j 7 imitations, sharp pharyngeal plane 4th figure ratio z (7) war Yahi Ida jI17') beast I Mutsu 1 @ face jump 3 figure conventional 49-II) Senmendai Yukaku

Claims (1)

[Claims] A second semiconductor region of the first conductivity type and a third semiconductor region of the second conductivity type are selectively provided on the first semiconductor region of the first conductivity type.
and a fourth semiconductor region of the first conductivity type are sequentially stacked, the third semiconductor region being a base region, one of the second and fourth semiconductor regions being a collector region, and the other being an emitter region. a first electrode connected to the fourth semiconductor region;
A heterojunction bipolar device characterized in that a base electrode connected to the third semiconductor region is interposed between the third electrode connected to the second semiconductor region via the semiconductor region. transistor.