JPS62116044A - Phase modulating system - Google Patents
Phase modulating systemInfo
- Publication number
- JPS62116044A JPS62116044A JP25593985A JP25593985A JPS62116044A JP S62116044 A JPS62116044 A JP S62116044A JP 25593985 A JP25593985 A JP 25593985A JP 25593985 A JP25593985 A JP 25593985A JP S62116044 A JPS62116044 A JP S62116044A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- phase
- clock
- discrimination
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
中継器のインサービス監視方式において、中継器内識別
回路−の出力側に第2の識別回路を設け、該第2の識別
回路に入力するクロック信号に位相変調を施すようにす
ることで、符号誤り率特性に悪影響を及ぼさないように
したものである。[Detailed Description of the Invention] [Summary] In an in-service monitoring system for a repeater, a second identification circuit is provided on the output side of an identification circuit within the repeater, and a phase difference is applied to a clock signal input to the second identification circuit. By applying modulation, it is possible to avoid adversely affecting the bit error rate characteristics.
本発明は、例えば、光中継器の符号誤り率等を監視する
監視情報を、主伝送クロック信号の位相変調によって端
局へ伝送するインサービス監視方式の位相変調方式の改
良に関する。The present invention relates to an improvement in a phase modulation method of an in-service monitoring method in which monitoring information for monitoring the code error rate of an optical repeater, etc., is transmitted to a terminal station by phase modulation of a main transmission clock signal, for example.
上記位相変調方式では、多中継伝送してアライメントジ
ッタが累積した場合にも、符号誤り率特性に悪影響を及
ぼさないことが望ましい。In the phase modulation method described above, it is desirable that the bit error rate characteristics not be adversely affected even when alignment jitter accumulates due to multiple repeat transmission.
第3図は従来例のブロック図、第4図は第3図の各部の
波形のタイムチャートで(A)(B)は第3図のa、b
点に対応している。Figure 3 is a block diagram of the conventional example, Figure 4 is a time chart of waveforms of each part in Figure 3, and (A) and (B) are a and b in Figure 3.
corresponds to the point.
図中1は識別回路、2はタイミング回路、3は位相変調
回路を示す。In the figure, 1 is an identification circuit, 2 is a timing circuit, and 3 is a phase modulation circuit.
中継器に送られてきたディジタル信号は、識別回路1に
ての識別点のS/Nを最良にする為の等化増幅器の帯域
幅により、波形が鈍り、識別回路1の入力では、第4図
(A)に示す如き受イ8側で発生した雑音を伴うアイパ
ターンの波形となる。The waveform of the digital signal sent to the repeater is blunted by the bandwidth of the equalizing amplifier to optimize the S/N of the discrimination point in the discrimination circuit 1, and at the input of the discrimination circuit 1, the waveform becomes dull. The eye pattern waveform is accompanied by noise generated on the receiver 8 side as shown in FIG. 8A.
この波形よりクロックをタイミング回路2にて抽出し、
第4図(B)の実線で示すクロックを出力する。The clock is extracted from this waveform by the timing circuit 2,
The clock shown by the solid line in FIG. 4(B) is output.
このクロックに位相変調回路3にて、例えば21KHz
位相変調幅P−Pが30度の位相変調を施し、この位相
変調されたクロックの立ら上がり点にて、識別回路1に
てOか1かの識別を行い、位相変調された識別結果を出
力することで、端局に中継器の監視情報を送信する。For example, 21KHz is applied to this clock in the phase modulation circuit 3.
Phase modulation with a phase modulation width P-P of 30 degrees is performed, and at the rising point of this phase-modulated clock, the discrimination circuit 1 discriminates between O and 1, and the phase-modulated discrimination result is By outputting, the monitoring information of the repeater is transmitted to the terminal station.
しかしながら、位相変調しない時の識別点は第4図のd
点で、アイパターンが広く多少ジッタがあっても符号識
別誤りを生じることはないが、位相変調して識別点がロ
、ハ点に移動するとアイパターンの狭いところで識別す
ることになり、雑音の影響も大きく、多中継伝送してア
ライメントジッタが累積した場合には、符号誤り率特性
に悪影響を及ぼす問題点がある。However, when there is no phase modulation, the discrimination point is d in Figure 4.
Even if the eye pattern is wide and there is some jitter, code identification errors will not occur. However, if phase modulation is used to move the identification point to points A and C, identification will occur in a narrow area of the eye pattern, which may cause noise. The influence is also large, and when alignment jitter accumulates due to multiple repeat transmission, there is a problem that it adversely affects the bit error rate characteristics.
上記問題点は、中継器内識別回路(1)の出力側に第2
の識別回路(4)を設け、該第2の識別回路(4)に入
力するクロック(8号に位相変調を施す(3)ようにし
た本発明の位相変調方式により解決される。The above problem is due to the fact that there is a second
This problem is solved by the phase modulation method of the present invention, in which a second identification circuit (4) is provided, and phase modulation is applied to the clock (No. 8) input to the second identification circuit (4).
本発明によれば、識別回路(1)により識別された波形
は雑音は除かれ又1の場合は矩形状の波形になる点に着
目し、これを入力する第2の識別回路(4)にて、位相
変調されたクロックで、識別することで位相変調するが
、この場合はクロックが位相変調のため移動しても、ア
イパターンは狭くならず、雑音もないので、多中継伝送
してアライメントジッタが累積した場合にも、符号誤り
率特性に悪影響を及ぼすことばなくなる。According to the present invention, the noise is removed from the waveform identified by the identification circuit (1), and in the case of 1, it becomes a rectangular waveform. In this case, even if the clock moves due to phase modulation, the eye pattern will not become narrower and there will be no noise, so alignment can be achieved by transmitting multiple times. Even if jitter accumulates, it will no longer have an adverse effect on the bit error rate characteristics.
第1図は本発明の実施例のブロック図、第2図は第1図
の各部の波形のタイムチャートで(A)〜(D)は第1
図のa w d点に対応している。Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a time chart of waveforms of each part in Fig. 1, and (A) to (D) are the first
This corresponds to points a w and d in the figure.
図中4は識別回路を示し、尚全図を通じ同一符号は同一
機能のものを示す。In the figure, numeral 4 indicates an identification circuit, and the same reference numerals indicate the same functions throughout the figures.
第1図で第3図の場合と異なる点は、識別回路1ではタ
イミング回路2の出力の第2図(B)に示す主伝送路の
クロックにて、第2図(A)に示す入力信号を、識別し
て、この識別された、第2図(C)に示す雑音もなく矩
形状となった波形を識別回路4に入力し、この入力信号
を、タイミング回路2の出力のクロックを位相変調回路
3にて位相変調した第2図(D)に示すクロックにて識
別するようにした点である。The difference between FIG. 1 and FIG. 3 is that the identification circuit 1 receives the input signal shown in FIG. 2(A) using the main transmission line clock shown in FIG. The identified rectangular waveform without any noise shown in FIG. The difference is that the clock shown in FIG. 2(D), which is phase-modulated by the modulation circuit 3, is used for identification.
即ら、識別回路4に入力する波形は第2図(C)に示す
如く雑音もなく矩形状の波形であるので、タイミング回
路2の出力のクロックが位相変調回路3にて位相変調さ
れ、識別点が二からホ。That is, since the waveform input to the identification circuit 4 is a rectangular waveform with no noise as shown in FIG. Dots from 2 to E.
へ点に移動しても、アイパターンは狭くならず、雑音も
ないので、多中継伝送してアライメントジッタが累積し
た場合にも、符号誤り率特性に悪影響を及ぼすことはな
い。Since the eye pattern does not become narrower even when moving to the 0 point, and there is no noise, even if alignment jitter accumulates due to multiple repeat transmission, there will be no adverse effect on the bit error rate characteristics.
以上詳細に説明せる如く本発明によれば、中継器の監視
情報を端局に伝送するために、位相変調されたクロック
信号にて識別した場合、多中継伝送してアライメントジ
ッタが累積した場合にも、符号誤り率特性に悪影響を及
ぼすことはなくなる効果がある。As explained in detail above, according to the present invention, when transmitting repeater monitoring information to a terminal station, identification is performed using a phase-modulated clock signal, and when alignment jitter accumulates due to multiple repeat transmissions. This also has the effect of eliminating any negative effects on the bit error rate characteristics.
第1図は本発明の実施例のブロック図、第2図は第1図
の各部の波形のタイムチャート、第3図は従来例のブロ
ック図、
第4図は第3図の各部の波形のタイムチャートである。
図において、
1.4は識別回路、
2はタイミング回路、
3は位相変調回路を示す。
小発朗の矢施jつの70ツ20
亭 1 口
羊1聞の各音部シ反す5のタイムチV−)−茅 2 圓Fig. 1 is a block diagram of the embodiment of the present invention, Fig. 2 is a time chart of waveforms of each part in Fig. 1, Fig. 3 is a block diagram of a conventional example, and Fig. 4 is a waveform diagram of each part of Fig. 3. This is a time chart. In the figure, 1.4 is an identification circuit, 2 is a timing circuit, and 3 is a phase modulation circuit. Kohatsurou's Yase jtsu 70 tsu 20 Tei 1 Kuchihitsu 1 mon each timbre of 5 timchi V-) - Kaya 2 En
Claims (1)
て端局へ伝送するインサービス監視方式において、 中継器内識別回路(1)の出力側に第2の識別回路(4
)を設け、該第2の識別回路(4)に入力するクロック
信号に位相変調を施す(3)ようにしたことを特徴とす
る位相変調方式。[Claims] In an in-service monitoring method in which repeater monitoring information is transmitted to a terminal station by phase modulation of a main transmission clock signal, a second identification circuit (4) is provided on the output side of the repeater internal identification circuit (1).
), and the clock signal input to the second identification circuit (4) is subjected to phase modulation (3).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60255939A JPH0618382B2 (en) | 1985-11-15 | 1985-11-15 | Phase change method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60255939A JPH0618382B2 (en) | 1985-11-15 | 1985-11-15 | Phase change method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS62116044A true JPS62116044A (en) | 1987-05-27 |
JPH0618382B2 JPH0618382B2 (en) | 1994-03-09 |
Family
ID=17285669
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60255939A Expired - Lifetime JPH0618382B2 (en) | 1985-11-15 | 1985-11-15 | Phase change method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0618382B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55938A (en) * | 1978-06-19 | 1980-01-07 | Toshiba Corp | Online monitor unit of sequnce controller |
-
1985
- 1985-11-15 JP JP60255939A patent/JPH0618382B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55938A (en) * | 1978-06-19 | 1980-01-07 | Toshiba Corp | Online monitor unit of sequnce controller |
Also Published As
Publication number | Publication date |
---|---|
JPH0618382B2 (en) | 1994-03-09 |
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