JPS62115792A - Semiconductor laser - Google Patents

Semiconductor laser

Info

Publication number
JPS62115792A
JPS62115792A JP25474585A JP25474585A JPS62115792A JP S62115792 A JPS62115792 A JP S62115792A JP 25474585 A JP25474585 A JP 25474585A JP 25474585 A JP25474585 A JP 25474585A JP S62115792 A JPS62115792 A JP S62115792A
Authority
JP
Japan
Prior art keywords
face
difference
semiconductor laser
region
light emitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25474585A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Sasaki
佐々木 義光
Shigeo Yamashita
茂雄 山下
Tadao Kaneko
金子 忠男
Yuichi Ono
小野 佑一
Takashi Kajimura
梶村 俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP25474585A priority Critical patent/JPS62115792A/en
Publication of JPS62115792A publication Critical patent/JPS62115792A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To realize a practically usable laser element whose end faces are produced through working processes other than the cleavage process, by coating the laser element unsymmetrically such that the auxiliary end face used only for monitor light or the like has a larger difference in level than the other end face. CONSTITUTION:End faces of light emission output surface are produced by wet etching and dry etching. In each of these end faces, levels are differed between the surface of the light emitting region and the surface of the other region. The difference in level (difference 1) between the light emitting region and the other region in the principal light emission end face is smaller than the difference in level (difference 2) between the light emitting region and the other region in the other end face. The difference 1 is 5mum or less, while the difference 2 is 10mum or less. A low reflection film 6 is provided on the end face with the smaller difference in level. A high reflection film 8 is provided on the end face with larger difference in level.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体レーザ装置の素子形状に関するものであ
り、特に量産化と実装に好適な素子形状に関するもので
ある。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an element shape of a semiconductor laser device, and particularly to an element shape suitable for mass production and packaging.

〔発明の背景〕[Background of the invention]

近来、半導体レーザの端面をへき開法以外のウェットエ
ツチング法(和田他、昭和59年度秋委応用物理学会講
演予稿集、13p−R−5,および渋谷他、信学技術E
D−84−95、第75頁参照)およびドライ加工法(
ジャパニーズ・ジャーナルオブ アプライド・フイドッ
クス、第24巻、1985年、第L463頁(S 、 
Semura at al、J、J、A、P、 Vol
、24. PL463.1985)による加工例の報告
があるが、これらは未だ実験段階で片端面のみを加工し
ているにすぎない。
Recently, wet etching methods other than the cleavage method have been applied to the end face of semiconductor lasers (Wada et al., Proceedings of the 1985 Autumn Conference of Japan Society of Applied Physics, 13p-R-5, and Shibuya et al., IEICE Technology E).
D-84-95, page 75) and dry processing method (see page 75)
Japanese Journal of Applied Physics, Volume 24, 1985, Page L463 (S,
Semura at al, J, J, A, P, Vol.
, 24. There are reports of processing examples according to PL463.1985), but these are still in the experimental stage and only one end surface is processed.

〔発明の目的〕[Purpose of the invention]

本発明の目的は半導体レーザの端面をへき開以外の加工
法で作製したものについて、実装に適した素子構造を提
供することにある。
An object of the present invention is to provide an element structure suitable for mounting a semiconductor laser whose end face is manufactured by a processing method other than cleaving.

〔発明の概要〕[Summary of the invention]

半導体レーザの端面をへき開法以外の加工によって作成
したものでは、エツチングによる段差が基板と加工面と
の間に生じ、この段差により、出射光の一部分が反射し
、実装時にF ar −F 1eldP attern
に乱れが起こる。本願発明は光を有効に利用する端面側
の段差を少なくし、モニター光程度にしか使わない端面
側の段差を大きくする素子構造にすることによって、こ
の問題を解決した。
When the end face of a semiconductor laser is fabricated by processing other than the cleavage method, a step is created between the substrate and the processed surface due to etching, and a portion of the emitted light is reflected by this step, resulting in F ar −F 1eldP attern during mounting.
disturbance occurs. The present invention solves this problem by creating an element structure in which the step on the end surface side, where light is used effectively, is reduced, and the step on the end surface side, which is used only for monitoring light, is increased.

また段差を少なくして光を有効に利用する端面側に低反
射膜コーティングし、段差が大きくモニター光程度にし
か使わない端面側に高反射膜コーティングした。すなわ
れ非対称コーティングをした素子構造にすることによっ
て、この問題を解決した。
Additionally, a low-reflection coating was applied to the end face, which has fewer steps and is used more effectively for light, and a high-reflection film was coated to the end face, which has a larger step and is only used as a monitor light. This problem was solved by creating an element structure with an asymmetric coating.

〔発明の実施例〕[Embodiments of the invention]

以下、本実施例を詳細に説明する。 This example will be described in detail below.

実施例1 半導体レーザはGat−xA Q llAl1ダフルへ
テロ接合構造を有する例を用いて説明する。第1図に示
す如くn形GaAs基板結晶1上にG ax−J Q 
XAsダブルへテロ接合エピタキシャル結晶2に成長し
、P形電極3.n形電極4をつけた。つぎにフォトレジ
ストをp形電極上3上に塗布しフォトリソグラフィ技術
により、端面加領域のパターンを焼付現像する。ここま
での工程で帯状のフォトレジスト膜5が形成される。つ
ぎにp形電極3をフォトレジスト5をマスクとして硝酸
第2セリウムアンモン:水=1 : 10の溶液でエツ
チング除去する。
Example 1 A semiconductor laser will be explained using an example having a Gat-xAQllAl1 duffle heterojunction structure. As shown in FIG. 1, G ax-J Q
An XAs double heterojunction epitaxial crystal 2 is grown, and a P-type electrode 3. An n-type electrode 4 was attached. Next, a photoresist is applied onto the p-type electrode 3, and a pattern in the end surface processing area is printed and developed using photolithography. Through the steps up to this point, a band-shaped photoresist film 5 is formed. Next, the p-type electrode 3 is removed by etching with a solution of ceric ammonium nitrate:water=1:10 using the photoresist 5 as a mask.

端面加工をアエットエッチングで加工する例について述
べる。ダブルへテロ結晶2を硫酸:過酸化水素:水(1
: 5 : 1)のエッチセントにて基板結晶1に到達
する深さまでエツチングする。この工程でほぼ垂直の溝
が完成され、レーザの発光出力取り出と用端面となる。
An example of end face processing using aet etching will be described. Double heterocrystal 2 was mixed with sulfuric acid: hydrogen peroxide: water (1
Etch to a depth that reaches the substrate crystal 1 at an etch center of: 5:1). In this process, a nearly vertical groove is completed, which will serve as the end surface for extracting the laser's light emission output.

つぎに不要となったフォトレジスト5を除去する。Next, the photoresist 5 that is no longer needed is removed.

つぎに第2図に示す如くウェハーの端に設けられた平担
な部分で、かつ端面加工した溝の片側の延長線上のとこ
ろ(点線で示す)にスクライバ−の尖端11を当て傷を
つける。これを各溝ごとに行いウェハー折り曲げて短冊
状の素子ができる。
Next, as shown in FIG. 2, a scratch is made by applying the tip 11 of the scriber to a flat part provided at the end of the wafer and on an extension line (indicated by a dotted line) on one side of the groove formed on the end surface. This is done for each groove and the wafer is bent to form strip-shaped elements.

さらに溝と直角方向にスクライブし単体の素子が完成す
る。ここまでの工程を終えた素子を第3図に示す。
Furthermore, a single element is completed by scribing in a direction perpendicular to the groove. FIG. 3 shows the device after completing the steps up to this point.

以上は端面加工法としてウェットエツチング法について
述べたがドライエツチング法でも同様に可能で、第1図
のウェハーをフォトレジスト5の耐ドライッチ性を増す
ために、Deep U V (U 1traViole
t)光を照射し、しかるのち180℃にてベーキングす
る。この試料をE CR(E 1ectronCycl
otron Re5onance)放電を用いたRIB
E(Reactive Ion Baam Etchi
ng)装置にセットしCQzガスを導入放電させ基板結
晶1に到達する深さまでエツチングする。その後の工程
は前記ウェットエツチングで記載したものと同じである
The above describes a wet etching method as an end face processing method, but a dry etching method is also possible.In order to increase the dry etch resistance of the photoresist 5, the wafer shown in FIG.
t) Irradiate with light and then bake at 180°C. This sample was subjected to E CR (E 1 ectron cycle).
otron Re5onance) RIB using discharge
E(Reactive Ion Baam Etchi)
ng) The device is set, and CQz gas is introduced and discharged to perform etching to a depth that reaches the substrate crystal 1. The subsequent steps are the same as those described for wet etching above.

但しフォトレジスト5の除去はOzプラズマアッシャを
用いる。
However, the photoresist 5 is removed using an Oz plasma asher.

第3図に示すレーザ素子の段差の少ない端面側、即ち左
側からのF or F 1ald P atternを
第4図の(a)に示す。段差の大きく右側の端面側から
のFar Field Patternを第4図(b)
に示す。これから分かるように片側のF ar F 1
eld P atternは全く乱れがなく、もう一方
のFar Field Patternには乱れが存在
する。半導体レーザをシステムに実装して使うとき、段
差の少ない端面側を実際に光を有効に使う側になるよう
に組立てて用いれば何ら問題が起こらず端面を加工で形
成したレーザ素子の実用化の問題が解決された。
FIG. 4(a) shows the front view of the laser device shown in FIG. 3 from the end face side with fewer steps, that is, from the left side. Figure 4(b) shows the Far Field Pattern from the right end face side with a large step.
Shown below. As you can see, F ar F 1 on one side
eld Pattern has no disturbance at all, and the other Far Field Pattern has disturbance. When a semiconductor laser is mounted and used in a system, if it is assembled and used so that the end face side with fewer steps is the side that actually uses light effectively, no problems will occur and it will be possible to put a laser element whose end face is formed by processing into practical use. Problem resolved.

本実施例はG a t−J 11 XA9ダブルへテロ
構造のものについて説明したが、結晶材料は何ら制限を
受けない。さらにレーザ素子の構造に関してはCS P
 (Channelad 5ubstrate Pla
ner)型、B H(B uriad Hetsros
tucture)型、めの他諸々の半導体レーザ素子な
ど何れについとも可能であることは明らかである。
Although this embodiment has been described with reference to the Ga t-J 11 XA9 double heterostructure, the crystal material is not limited in any way. Furthermore, regarding the structure of the laser element, CSP
(Channelad 5ubstrate Pla
ner) type, B H (B uriad Hetsros
It is obvious that the present invention is possible with any type of semiconductor laser device, such as a laser diode (structure) type or a variety of other semiconductor laser devices.

実施例2 実施例1と同様に導体レーザはG a 1−xA Q 
XAsダブルへテロ接合構造を有する例を用いて説明す
る。第1図に示す如くn形GaAs基板結晶1上にGa
t−xA Q XAsダブルへテロ接合エピタキシャル
結晶2に成長し、p形電極3.ni電極4をつけた。
Example 2 As in Example 1, the conductor laser is G a 1-xA Q
This will be explained using an example having an XAs double heterojunction structure. As shown in FIG.
t-xA Q XAs double heterojunction epitaxial crystal 2 is grown, p-type electrode 3. Ni electrode 4 was attached.

つぎにフォトレジストをp形電極上3上に塗布とフォト
リソグラフィ技術により、端面加領域のパターンを焼付
現像する。ここまで工程で帯状のフォトレジスト[5が
形成される。つぎにp形電極3をフォトレジスト5をマ
スクとして硝酸第2セリウムアンモン:水=1 : 1
0の溶液でエツチング除去する。
Next, a photoresist is applied onto the p-type electrode 3, and a pattern of the end surface processing area is printed and developed using photolithography. In the steps up to this point, a band-shaped photoresist [5] is formed. Next, the p-type electrode 3 is formed using the photoresist 5 as a mask, and the mixture is ceric ammonium nitrate:water=1:1.
Remove by etching with 0 solution.

端面加工をウェットエツチングで加工する例について述
べる。ダブルへテロ結晶2を硫酸:過酸化水素:水(1
: 5 : 1)のエッチャントにて基板結晶1に到達
する深さまでエツチングする。この工程でほぼ垂直の溝
が完成され、レーザの発光出力取り出し用端面となる。
An example of end face processing using wet etching will be described. Double heterocrystal 2 was mixed with sulfuric acid: hydrogen peroxide: water (1
:5: Etching is performed using an etchant of 1) to a depth that reaches the substrate crystal 1. In this process, a nearly vertical groove is completed, which will become the end face for extracting the laser's light output.

つぎに不要となったフォトレジスト5を除去する。Next, the photoresist 5 that is no longer needed is removed.

以上は端面加工法としてウェットエツチング法について
述べたがドライエツチング法でも同様に可能で、第1図
のウェハーをフォトレジスト5の耐ドライツチ性を増す
ために、 Deep UV(Ultra Violet
)光を照射し、しかるのち180℃にてベーキングする
。この試料をECR(Electron Cyclot
ron Re5onance)放電を用いたRIBE 
(Reactive I on B eam E tc
hing)装置にセットしCQ 2カスを導入放電させ
基板結晶1に到達する深さまでエツチングする。この工
程でほぼ垂直の溝が完成され、レーザの発光出力取り出
し用端面となる。つぎに不要となまったフォトレジスト
5をOXプラズマアッシャ装置にて除去する。
The above describes a wet etching method as an edge processing method, but a dry etching method is also possible.In order to increase the dry etching resistance of the photoresist 5, the wafer shown in FIG.
) Irradiate with light and then bake at 180°C. This sample was subjected to ECR (Electron Cyclot
RIBE using discharge (ron Re5onance)
(Reactive I on Beam Etc
hing), and the CQ 2 scum is introduced and discharged to a depth that reaches the substrate crystal 1. In this process, a nearly vertical groove is completed, which will become the end face for extracting the laser's light output. Next, the unnecessary photoresist 5 is removed using an OX plasma asher device.

ここまでの工程を終えたウェハーを低反射膜被着を目的
として真空蒸着装置にセットし、電子ビーム蒸着により
5iOzを第5図に示す如くウェハーに対して斜め方向
から端面にp / 4 n 1被着する。
The wafer that has undergone the steps up to this point is placed in a vacuum evaporation device for the purpose of depositing a low-reflection film, and 5iOz is deposited on the end face from an angle to the wafer at a p/4 n 1 concentration using electron beam evaporation as shown in Figure 5. to adhere to.

ここでPはレーザの発振波長、nlは5iOzの屈折率
である。第5図において7は5i(h粒子を模式的に描
いたものであり、6は端面およびウェハーの電極3に被
着した5iOz膜を表わしている。つぎに高反射膜を目
的として第6図に示す如く低反射膜コートした端面の反
対側の端面に5iOzをλ/4nt、つぎにSiをλ/
4n2被着する。ここでn2はSiの屈折率である。第
6図において9は5LOzおよびSiの粒子を模式的に
表わしたものであり、8は5xOz+ S xからなる
高反射膜を表わしている。
Here, P is the oscillation wavelength of the laser, and nl is the refractive index of 5iOz. In FIG. 5, 7 is a schematic drawing of a 5i (h particle), and 6 represents a 5iOz film deposited on the end face and the electrode 3 of the wafer. As shown in the figure, 5iOz was applied to the end surface opposite to the end surface coated with the low reflection film for λ/4nt, and then Si was applied for λ/4nt.
4n2 deposited. Here, n2 is the refractive index of Si. In FIG. 6, 9 schematically represents particles of 5LOz and Si, and 8 represents a high reflection film made of 5xOz+Sx.

つぎに第7図に示す如くフォトリソグラフィ技術により
、加工端面の溝の中をフォトレジスト10で埋め込み、
p形電極3上に被着した不要な絶縁膜6,8をHF:N
H番F (1: 6)エツチング液にて除去する。しか
る後フォトレジスト10を除去する。
Next, as shown in FIG. 7, the grooves on the processed end surface are filled with photoresist 10 using photolithography technology.
Unnecessary insulating films 6 and 8 deposited on the p-type electrode 3 are removed with HF:N.
Remove with H No. F (1:6) etching solution. Thereafter, the photoresist 10 is removed.

つぎに第8図に示す如くウェハーの端に設けられた平担
な部分でかつ端面加工した溝の片側の延長線上のところ
(点線で示す)にスクライバ−の先端を当て傷をつける
。これを各溝ごとに行いウェハーを折り曲げて短冊状の
素子ができる。さらに溝と直角方向にスクライブし単体
の素子が完成する。ここまでの工程を終えた素子を第9
図に示す。
Next, as shown in FIG. 8, a scratch is made by applying the tip of a scriber to a flat part provided at the end of the wafer and on an extension line (indicated by a dotted line) on one side of the groove formed on the end surface. This is done for each groove and the wafer is bent to form strip-shaped elements. Furthermore, a single element is completed by scribing in a direction perpendicular to the groove. The device that has completed the steps up to this point is the 9th
As shown in the figure.

第9図に示すレーザ素子の段差の少ない端面側、即ち低
反射側からの光出力の例を第10図の12に示す。また
F ar F 1eld P atternの例を第4
図(a)と同様になる。段差の大きい端面側即ち高反射
膜側からの光出力の例を第10図の13に示す、またF
 ar F 1eld P atternの例を第4図
(b)と同様になる。これから分かりように片側から大
きな光出力が出射し、かつF ar F 1eld P
 atternは全く乱れない、もう一方からは光出力
が小さく。
12 shows an example of the optical output from the end face side with fewer steps, that is, the low reflection side of the laser element shown in FIG. 9. In addition, the example of F ar F 1eld P atttern is shown in the fourth example.
The result will be similar to that shown in Figure (a). An example of the light output from the end face side with a large step difference, that is, the high reflection film side is shown in 13 in Fig. 10, and F
The example of ar F eld P attern is similar to that shown in FIG. 4(b). As you can see, a large light output is emitted from one side, and F ar F 1eld P
Attern is not disturbed at all, and the light output from the other is small.

かつF ar F 1eld P atternには乱
れが左右する。
Moreover, the disturbance affects the F ar F eld P attern.

半導体レーザをシステムに実装して使うとき、低反射膜
側を実際に光を有効に使う側になるように組立てて用い
れば何ら開運が起こらず、端面を加工法で形成し、かつ
非対称コートを施したレーザ素子の実用化の問題が解決
された。
When a semiconductor laser is mounted and used in a system, if it is assembled and used so that the low-reflection film side is the side that actually uses light effectively, no problems will occur. The problem of putting the laser device into practical use has been solved.

本実施例はG a 1−XA Q Jsダブルへテロ構
造のものについて説明したが、結晶材料は何ら制限を受
けない。さらにレーザ素子の構造に関してはCS P 
(Channeled 5ubtrate Plana
r)型、BH(B uriad Heterostru
cture)型、めの他諸々の半導体レーザ素子など何
れについても可能である。
Although this embodiment has been described with respect to a Ga 1-XA Q Js double heterostructure, the crystal material is not limited in any way. Furthermore, regarding the structure of the laser element, CSP
(Channeled 5ubtrate Plana
r) type, BH (B uriad Heterostru
It is also possible to use any type of semiconductor laser device, such as a 3D (curve) type or other types of semiconductor laser devices.

また両端面加工の例について説明したが、片端面が加工
で、もう一方はへき開法のものについても同様に可能で
ある。また低反射膜として5iOzλ/4ns、高反射
膜5iOz、5L2WJの例にライて説明したが、これ
以外の材料、例えばAQxOδ。
Although an example of processing both end faces has been described, it is similarly possible to process one end face and cleave the other end face. Furthermore, although the explanation has been given using examples of 5iOzλ/4ns as a low reflection film and high reflection films 5iOz and 5L2WJ, other materials such as AQxOδ may be used.

5iaN番+非晶質Si、水素含有非晶質Siでも可能
であり、低反射膜の膜厚がλ/4nxより多少ずれでた
、また高反射膜として4層膜でも可能である。またウェ
ハー状態で非晶質コートした別について説明したが、短
冊状またはチップ化した後の素子について非晶質コート
しても可能であることは明らかである。
5iaN + amorphous Si or hydrogen-containing amorphous Si is also possible, the thickness of the low reflection film is slightly deviated from λ/4nx, and a 4-layer film is also possible as a high reflection film. Further, although the explanation has been given on the case where the wafer is coated with an amorphous material, it is clear that it is also possible to coat the device with an amorphous material after it has been formed into a strip or a chip.

〔発明の効果〕〔Effect of the invention〕

へき開以外の加工法で両端面を作製したレーザ素子のウ
ェハーを横通にチップ化すると、チップ化のときの切断
面と端面加工面との間の段差が両端面側に生じる。従っ
て両面のF ar F 1eldP atternに乱
れが生じるが、本発明は意図的にこの段差が片側だけに
生じるようにチップの切断を行い、F ar F 1e
ld P atternの乱れを片端面のみに抑えるも
ので、システムに半導体レーザを実装して使うとき、実
際に光を有効に利用するのは一方のみであるという用途
に好都合な構造であり、加工法で端面を作製したレーザ
素子の実用化を可能するという効果がある。
When a wafer of a laser device whose both end faces are fabricated by a processing method other than cleavage is turned into chips in a crosswise manner, a difference in level between the cut surface and the end face processed surface at the time of chip formation occurs on both end faces. Therefore, disturbance occurs in the F ar F 1eldP attern on both sides, but in the present invention, the chip is intentionally cut so that this level difference occurs only on one side.
This structure suppresses the disturbance of the LD pattern to only one end face, and when a semiconductor laser is mounted in a system, the structure is convenient for applications in which only one side actually uses light effectively, and the processing method This has the effect of making it possible to put into practical use a laser device whose end facets are fabricated using the method described above.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す半導体レーザウェハー
の斜視図、第2図は端面加工したウェハーをスクライブ
しているところの斜視図、第3図はチップ化された半導
体レーザ素子の斜視図、第4図は第3図のレーザ素子か
らの出射光の遠視野像、第5図は端面加工し°たウェハ
ーに低反射膜をコートしている横断面図、第6図はウェ
ハーに高反射膜をコートしている横断面図、第7図はウ
ェハーの端面溝にフォトレジ膜が埋め辺まれた横断面図
、第8図はウェハーをスクライブしているところの斜視
図、第9図はチップ化された半導体レーザ素子の斜視図
、第10図はレーザ素子の電気・光学特性の1例を示す
図である。 1− n形GaAs基板、 2− G al−x A 
Q x A sダブルへテロ成長層、3・・・p形電極
、4・・・n形電極、5・・・フォトレジスト、6・・
・低反射膜、7・・・低反射膜用粒子、8・・・高反射
膜、9・・・高反射膜粒子、10・・・フォトレジスト
、11・・・スクライブ−の先端。
Fig. 1 is a perspective view of a semiconductor laser wafer showing an embodiment of the present invention, Fig. 2 is a perspective view of a wafer whose end face has been processed and is being scribed, and Fig. 3 is a perspective view of a semiconductor laser element made into chips. Figure 4 is a far-field image of the emitted light from the laser element in Figure 3, Figure 5 is a cross-sectional view of a wafer whose end face has been processed and coated with a low-reflection film, and Figure 6 is a cross-sectional view of the wafer. Figure 7 is a cross-sectional view of the wafer being coated with a high-reflection film, Figure 7 is a cross-sectional view of the edges of the wafer edge groove filled with a photoresist film, Figure 8 is a perspective view of the wafer being scribed, Figure 9 The figure is a perspective view of a chipped semiconductor laser device, and FIG. 10 is a diagram showing an example of the electrical and optical characteristics of the laser device. 1- n-type GaAs substrate, 2- Gal-x A
Q x A s double hetero growth layer, 3...p-type electrode, 4...n-type electrode, 5...photoresist, 6...
- Low reflective film, 7... Particles for low reflective film, 8... High reflective film, 9... High reflective film particles, 10... Photoresist, 11... Tip of scribe.

Claims (1)

【特許請求の範囲】 1、発光出力面の両端面をウエツトエツチング、ドライ
エツチングで作成した、該端面に発光領域の面とそれ以
外の領域の面に段差がある。半導体レーザにおいて、主
な発光端面における発光領域とそれ以外の領域の面との
段差(段差1)から、他方の端面における発光領域とそ
れ以外の領域の面との段差(段差2)より小さいことを
特徴とした半導体レーザ。 2、上記段差1が5μm以下であり、上記段差2が10
μm以下であることを特徴とする特許請求の範囲第1項
記載の半導体レーザ。 3、半導体レーザの発光出力面をなす片端面、もしくは
両端面に発光領域の面と、それ以外の領域の面とに段差
がある半導体レーザにおいて、段差の少ない方の端面に
低反射膜を有し、段差の多い端面に高反射膜を有するこ
とを特徴とした半導体レーザ。
[Claims] 1. Both end faces of the light emitting output surface are created by wet etching and dry etching, and the end faces have a step between the light emitting region surface and the other region surface. In a semiconductor laser, the difference in level (step 1) between the light emitting region and the surface of the other region at the main light emitting end facet is smaller than the difference in step (step 2) between the light emitting region and the surface of the other region at the other end facet. A semiconductor laser featuring 2. The step 1 is 5 μm or less, and the step 2 is 10 μm or less.
2. The semiconductor laser according to claim 1, wherein the semiconductor laser has a diameter of μm or less. 3. In a semiconductor laser that has a step between the light emitting region surface and the other region surface on one end surface or both end surfaces forming the light emitting output surface of the semiconductor laser, a low reflection film is provided on the end surface with fewer steps. A semiconductor laser characterized by having a highly reflective film on an end face with many steps.
JP25474585A 1985-11-15 1985-11-15 Semiconductor laser Pending JPS62115792A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25474585A JPS62115792A (en) 1985-11-15 1985-11-15 Semiconductor laser

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25474585A JPS62115792A (en) 1985-11-15 1985-11-15 Semiconductor laser

Publications (1)

Publication Number Publication Date
JPS62115792A true JPS62115792A (en) 1987-05-27

Family

ID=17269279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25474585A Pending JPS62115792A (en) 1985-11-15 1985-11-15 Semiconductor laser

Country Status (1)

Country Link
JP (1) JPS62115792A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53120291A (en) * 1977-03-29 1978-10-20 Nec Corp Manufacture of semiconductor laser
JPS6055686A (en) * 1983-09-06 1985-03-30 Nec Corp Distributed feedback type semiconductor laser
JPS6298787A (en) * 1985-10-25 1987-05-08 Fujitsu Ltd Manufacture of semiconductor laser

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53120291A (en) * 1977-03-29 1978-10-20 Nec Corp Manufacture of semiconductor laser
JPS6055686A (en) * 1983-09-06 1985-03-30 Nec Corp Distributed feedback type semiconductor laser
JPS6298787A (en) * 1985-10-25 1987-05-08 Fujitsu Ltd Manufacture of semiconductor laser

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