JPS6211376A - Phase adjusting circuit for keying signal - Google Patents

Abstract

PURPOSE:To form a variable delay circuit with an inverter to an integrating circuit and to eliminate the influence of temperature variation by independently adjusting the leading edge and the trailing edge of a keying signal and by making the said edges coincide with those of a video signal to be extracted. CONSTITUTION:A keying signal (a) by which an image signal from three-primary color signal input terminals 3-5 is processed is outputted from the key generator 6 of the titled circuit, and the signal is supplied to the first variable delay circuit 12. The circuit 12 gives the signal (a) a delay in an amount that its trailing edge coincides on the rear end of an object-image signal (f), and the output signal is made a signal (b) which is delayed by the second delay circuit 13 so that its leading edge coincides on the front end of the signal (f). The output from the circuit 13 is made a signal (c), which is supplied with the signal (b) outputted by the circuit 12 to a multiplier 14. The multiplier 14 adjusts the phases of the said signals and generates a signal (d) to supply it as a switching pulse to an analog switch circuit 8. The circuits 12 and 13 are of such construction that two pairs of an integrating circuit and an inverter to invert the output thereof are longitudinally connected. The constitution of the titled circuit is is thus simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a keying signal phase adjustment circuit, and in particular to a keying signal phase adjustment circuit.
This invention relates to phase adjustment of leading and trailing edges of a keying signal in a chromakey video switching device (special effects amplifier) that switches two video signals depending on the background color.

BACKGROUND OF THE INVENTION FIG. 6 shows a block diagram of an example of a conventional chromakey video switch. In the same figure, the input terminal 1 is connected to a first image as shown in FIG. video signal is received. On the other hand, a second video signal that is to become the background of the subject image is input to the input terminal 2 by video switching. Further, three primary color signals of red (R), green (G) and blue (B) regarding the same video information as the first video signal are input to the input terminals 3, 4 and 5, and are supplied to the key generator 6. be done.

The key generator 6 arbitrarily selects a primary color signal to obtain a keying signal from the input three primary color signals, and for example, when the background color is blue, the key generator 6 compares the blue signal with an arbitrary slice level shown by a broken line ■ in FIG. 7(B). However, a keying signal as shown in (Δ) in the figure is generated and outputted, which is at a high level in the subject image area indicated by diagonal lines (■) in the figure (B), which has a different hue from the blue background color part I. In addition, Fig. 7 (
B) shows the first video signal for convenience.

The keying signal as shown in FIG. 7(A) taken out from the key generator 6 is supplied to an analog switching circuit 8 through a variable delay line 7, and then through fixed delay lines 9 and 10 for mutual time adjustment. The first.
Of the second video signals, the first video signal (the subject image) is selectively output during the period when the keying signal is at a high level, while the second video signal is selectively output during the period when the keying signal is at a low level. . As a result, the output terminal 11
In this case, a composite video signal is extracted in which the subject image in the first video signal is embedded in the second video signal.

Problems to be Solved by the Invention However, in the above-mentioned conventional device, by varying the delay slip of the keying signal (adjusting the phase of the keying signal) using the variable delay line 7, the first and second video signals are Although time alignment with the keying signal was performed, it was difficult to arbitrarily set the pulse width of the keying signal, and the variable delay line 7 also became large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a keying signal phase adjustment circuit that solves the above problems by supplying each output signal of two cascade-connected variable delay circuits to a multiplier.

Means for Solving the Problems A keying signal phase adjustment circuit according to the present invention comprises a first variable delay circuit to which a keying signal is supplied, a second variable delay circuit to which an output signal thereof is supplied, and a second variable delay circuit to which an output signal thereof is supplied. 1st and 2nd
The multiplier is supplied with the output signals of the variable delay circuits and outputs their multiplied output signals as keying signals.

After the active keying signal is trailing edge phased by the first variable delay circuit, it is supplied to the second variable delay circuit where its leading edge phase is phased.

The output signals of the first and second variable delay circuits are supplied to a multiplier, where they are ANDed and output as a keying signal.

Note that if the first and second variable delay circuits are configured by two cascade-connected circuits each consisting of an integrating circuit and an inverter that inverts the polarity of the output signal, the first and second variable delay circuits can be continuously variable and have humidity characteristics. It can be improved.

ACTUAL EXAMPLE Hereinafter, an embodiment of the circuit of the present invention will be described in detail with reference to FIGS. 1 to 5.

FIG. 1 shows a block system diagram of an embodiment showing the circuit of the present invention together with a chromakey video switch. In the figure, the same components as those in FIG. 6 are denoted by the same reference numerals, and the explanation thereof will be omitted as appropriate. As shown in FIG. 7 (Δ>, (B)), the keying signal a shown in FIG. Also, the restoration position is temporally later than the end of the object image part (2), and the high level period of the keying signal a extends over a wider range than the object image part.This keying signal a is transmitted to the first variable delay circuit. 12, the signal is then delayed by a predetermined amount so that the trailing edge coincides with the end of the object image signal f as shown in FIG. The signal C is delayed by a predetermined amount so that the leading edge coincides with the starting edge of the subject image signal f.

The multiplier 14 constitutes a keying signal phase adjustment circuit together with the variable delay circuits 12 and 13 described above, and the signal d as shown in FIG.
is supplied to the analog switching circuit 8 as a switching pulse. On the other hand, the first video signal shown as e in FIG. 2 that has entered the input terminal 1 is delayed by a fixed delay line 9 for a certain period of time to become the signal shown in FIG. . As a result, the analog switching circuit 8 receives the input signal f.
The signal f is selectively outputted to the output terminal 11 only during the high level period of the keying signal d whose leading and trailing edges are matched by phase adjustment.

Here, the first and second variable delay circuits 12 and 13 are
They each have the same configuration, for example, as shown in Figure 3,
It has a configuration in which two sets of circuits each consisting of an integrating circuit and an inverter are connected in cascade. A pulse having a width T+ as shown in FIG. 4 (△) that enters the input terminal 16 is integrated by a first integrating circuit consisting of a resistor R1 and a capacitor C1 to form a waveform as shown in FIG. 4 (B). After that, inverter 17
supplied to Here, since the threshold value of the inverter 17 at room temperature is shown by the dashed line in FIG. 4(B), its output signal becomes as shown in FIG. 4(C). The output pulses of the inverter 17 are integrated by a second integrating circuit consisting of a resistor R2 and a capacitor C2 to form a waveform as shown in FIG. 4(D), and then supplied to the inverter 18.

The threshold value of the inverter 18 at room temperature is shown by the dashed line in FIG. A time-delayed pulse is output.

Here, if the temperature differs greatly from room temperature, as shown in Figure 5 (
As shown in A), an input pulse of the same width T+ is input to the input terminal 16.
Even if the inverter 17 enters the
As shown by the one-point @ line, the temperature is lower than that at room temperature, so the low level period of the output pulse of the inverter 17 becomes longer (the pulse width becomes wider). As a result, the inverter 18
The input signal of is as shown by the solid line in Fig. 5(D),
As the threshold value of the inverter 18 is lower than that at room temperature, for example, as shown by the dashed line in the figure (D>), the inverter 18
The high level period of the output pulse No. 8 becomes shorter (the pulse width becomes narrower), and in the end, the Toil! The extended pulse shown in FIG. 5(E) is extracted. Therefore, the variable delay circuits 12 and 13 having the configuration shown in FIG. 3 have a circuit configuration in which the output pulses of the preceding and succeeding circuits act as phase-advanced and phase-delayed circuits, cancel each other out, and are hardly affected by temperature changes. Furthermore, the conventional variable delay line 7 has been made large in size due to the configuration using a lumped constant circuit using a varicap or mechanical switching, but in this embodiment, the circuit configuration can be made smaller because it is composed of an integrating circuit using a CR and an inverter.

Note that the fixed delay lines 9 and 10 can be omitted by using a delay by an NTSC encoder.

Effects of the Invention As described above, according to the present invention, the phases of the leading edge and trailing edge of the keying signal can be adjusted independently, and as a result, the leading edge and the trailing edge of the keying signal can be adjusted at the beginning and end of the video signal to be handled. Also, since the variable delay circuit has a configuration in which two circuits each consisting of an integrating circuit and an inverter are connected in cascade, the circuit can be made smaller compared to a conventional variable delay line, and it can also be made more stable due to temperature changes. This has the advantage of being able to have a configuration that is almost unaffected by this.

[Brief explanation of the drawing]

FIG. 1 is a block system diagram of an embodiment showing the circuit of the present invention together with a chromakey video switch, FIG. 2 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1, and FIG. 3 is a block system diagram of the block system shown in FIG. 1. 4 and 5 are signal waveform diagrams for explaining the operation of the circuit shown in FIG. 3, and FIG. 6 is a block diagram showing an example of a conventional chromakey video switcher. System diagram, FIG. 7 is a signal waveform diagram for explaining the operation of the block system shown in FIG. 1.2... Video signal input terminal, 3, 4.5... Three primary color signal input terminal, 6... Key generator, 8...
Analog switching circuit, 11... composite video signal output terminal,
12... First variable delay circuit, 13... Second variable delay circuit, 14... Multiplier. Patent applicant Victor Company of Japan Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (2)

[Claims] (1) A first variable delay circuit to which a keying signal is supplied and adjusts the phase of the trailing edge; and a second variable delay circuit to which the output signal of the first variable delay circuit is supplied and adjusts the phase of the leading edge. and a multiplier that is supplied with both output signals of the first and second variable delay circuits and outputs their multiplied output signal as a keying signal. (2) The first and second variable delay circuits each have a configuration in which two circuits each consisting of an integrating circuit and an inverter that inverts the polarity of the output signal of the integrating circuit are connected in cascade. A keying signal phase adjustment circuit according to claim 1.