KR820001556B1 - Electronic signal processing apparatus - Google Patents

Abstract

A charge coupled device(CCD) comb filter arrangement is provided which is particularly suited for separating luminance and chrominance signal components in a color TV signal. Parallel paths of long and short CCD delay lines(26) (32) using a common clock drive are provided in which the difference in delay between the long and short lines determines the frequency intervals between the teeth of the comb substantially independently of factors of other than the clock frequency and the number of delay stages.

Description

Electric signal processing device

One embodiment of the electric signal processing apparatus according to the present invention is a configuration diagram showing a part of the actual circuit type and the other part of the block type.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit arrangement for processing periodic electrical signals, and more particularly, to a circuit arrangement for processing color television signals to impart a comb filter, precision augmentation, a combination of comb filter and precision augmentation or other functions.

Electric signals with periodic properties can be effectively processed by accumulating replicas of signals separated in time by repetition periods, and then synthesizing the accumulated replicas to enhance the information content of the signals. have. For example, in a typical television broadcasting system (and most recording / reproducing systems), most of the bright (luminance) information contained in an image is arranged so as to be represented by a signal frequency concentrated at a frequency that is approximately an integer multiple of the horizontal scanning frequency. . Color (color) information is coded or inserted into the luminance signal spectrum about a frequency at a position half of an integer multiple of the prescan frequency (that is, an odd multiple of 1/2 of the prescan frequency).

The color information and the luminance information can be separated, and the information representing the precision portion is augmented by properly synthesizing the synthesized signal spectrum. Known synthesized circuit configurations have a radix relationship between the color signal component and 1/2 of the scanning frequency, thereby extracting the color signal component for the corresponding video region on each line which appears as a 180 ° out-of-phase (so-called interlaced frequency component) sequence. It is advantageous that it can be done. The luminance signal components for the corresponding image regions on successive linear lines are substantially in phase relationship (non-interlaced) with each other.

The comb-type filter device can generate one or more replicas of the composite video display signal that are delayed in time (so-called 1H delayed) only at least one set of pre-scanning periods. The interlaced frequency component (e.g., color component) is canceled by adding the signal from a set of lines with the signal from the preceding line, while the non-interlaced frequency component (e.g., luminance component) is augmented. It is also possible to cancel the non-interlaced frequency component by subtracting the signal of two consecutive lines (inverting the signal for the first line and adding it with the signal for the second line) while increasing the interlaced frequency component. It may be. In this way, the luminance signal and the color signal are comb-filtered with each other, whereby both can be advantageously separated. Many circuits have been proposed as comb filter devices of the type such as vertical aperture correction devices using one or more 1H delay devices. These circuits are described, for example, in the specifications of US Pat. Nos. 2,729,698, 2,885,573, 2,957,042, 2,971,053, 3,030,440, 3,546,372, 3,546,490, 3,996,606 and 3,996,610.

The device of this type is shown in the simple form of a pair of directly connected non-delayed lines, conventionally shown as simple conductors, and a second delayed line including a 1H delay device, each signal path being a single adder or subtractor. Is coupled to the input. However, in an actual device, the delay signal path usually has a separate adjustable delay element, and the signal delay introduced by the actual circuit elements such as the amplifier and the signal addition or subtraction device input circuit is essentially introduced into the non-delay path. Matching. In many well-known types of 1H delay devices, it is difficult to accurately predict or control the delay of the 1H delay device itself, and for this reason, it is necessary to provide a trimming delay device that can be adjusted to either or both sides of the line.

If the delay device requires time sampling of the delayed signal, a filter is sometimes required in the delay line to remove the sampling waveform. The filter itself is delayed and makes some changes in the amplitude responsiveness of the delayed signal. This factor makes it necessary to add an adjustable compensating element in the comb filter device.

When designing comb filters or devices of the same type, it is necessary to consider extensively the ambient conditions and temperature characteristics that affect the delay device and the accompanying circuits.

An apparatus for processing an electrical signal according to an embodiment of the present invention is an input signal comprising at least a first information component and at least a portion of the frequency spectrum of the information component is a plurality of frequencies separated by the same difference from the first frequency. And means for supplying said input signal with signal energy concentrated in its vicinity. Further, means for supplying a clock signal at a frequency proportional to the first frequency is also provided. At least first and second signal processing lines are provided, each having a signal input portion coupled to the input signal supply means and an output portion of the delayed signal. The first and second tracks contain different numbers of signal delay stages. The signal delay end transmits a signal representing the input signal between the input and output in response to the clock signal. The first and second lines give a time delay difference proportional to the difference in the number of stages in the two lines in inverse proportion to the frequency of the clock signal. A signal synthesizing means is coupled to the delay signal output portion of each line to produce a synthesized signal having a comb-like frequency spectrum with signal components appearing at their maximum points periodically separated by the first frequency. A filter means is coupled to the output of the signal synthesizing means to pass a frequency band including a frequency related to the first information component.

In a particular embodiment of the present invention, the input signal is a composite color television signal comprising a luminance information component and a color information component. The high frequency portion of the luminance information includes a periodic frequency spectrum with respect to frequency and includes a maximum point separated by the horizontal scanning frequency. Color information is inserted between the maximum points of the luminance signal in the high frequency portion of the luminance signal band. The luminance information, the color information and the low frequency vertical detail information are separated by comb filter means having appropriate band selective filter characteristics.

Hereinafter, the present invention will be described with reference to the drawings. The figure shows a portion of a color television receiver suitable for processing signals suitable for NTSC, i.e., standard broadcast. Portions of the device that are typically described but not described elsewhere are described, for example, in CCI Color Television Service Data, C-6, 1976, issued by RCA Corporation in Indianapolis, Indiana, USA. Such a circuit configuration can be used.

The composite color television video signal including the luminance signal component and the color signal component is supplied by the television processing circuit 10. The television processing circuit 10 has, for example, a normal radio frequency amplifier stage, an intermediate frequency amplifier stage, and an image detector. As described above, the luminance signal component and the color signal component having a relationship between the frequency interlaces are supplied to the input terminal 14 of the signal processing device 16 shown in dotted lines via the capacitor 12. The dotted line portion has a circuit element that can be configured entirely on an N-MOS type single plate integrated circuit.

The composite video signal is supplied from the terminal 14 to the luminance signal comb filter 18 having the first and second signal paths 20 and 22. The signal paths 20 and 22 are configured such that the same nominal delay (1H delay) occurs in one horizontal scan line period in the signal delay amount. The signal path 20 includes an attenuator, i.e., a fractional gain amplifier (a gain of less than 1) 24, a signal delay line 26, and one input portion of the signal adder 28. Delay line 26 is intended to delay only a relatively short time (e.g., a fraction of a period of 1H) to a signal in the baseband, i.e., the image frequency range (e.g., from 0 to 5 MHz). It works. The signal path 22 delays the attenuator, i.e., the fractional gain amplifier 30 and only a predetermined time interval (only larger than the delay amount of the delay line 26, equal to 1H) in the same form as the signal path 20. And a basic band signal delay line 32 that operates to make it work. The comb filtered signal is supplied from the output of the addition circuit 28 to the filter compensation delay circuit 34, and then the output is supplied to the sampling and hold detection amplifier 36. The output signal from the sampling hold detection amplifier 36 is supplied to the low pass filter 40 via the terminal 38. The comb-filtered luminance signal output obtained from the low pass filter 40 is supplied to the signal synthesis matrix 42 (shown as a resistance matrix in the embodiment) and synthesized with the vertical detail signal described in the following procedure.

The composite video signal obtained from the terminal 14 is also supplied to the color signal comb filter 44 which shares a part of the signal path 22. In addition, the filter 44 has a signal path 46 and a separate circuit component as described later.

The two signal paths associated with the color signal comb filter 44 are in the same manner as the signal path of the luminance signal comb filter 18 so that the same difference is given to the delay amount of the signal in the one-line scanning period. The signal path 46 includes an inverted fraction gain amplifier, that is, an attenuator 48, and an input portion of the signal delay line 50 and the signal addition circuit 52 substantially the same as the delay line 26. The second input of the addition circuit 52 is coupled to the second output from the delay line 32. Two outputs of the delay line 32 generate substantially the same signal.

The comb-filtered signal is supplied from the output of the addition circuit 52 to the sample hold detection amplifier 54 having the same form as the sample hold detection amplifier 36. The first signal from the sample hold detection amplifier 54 is supplied to the low pass filter 58 via terminal 56. The low pass filter 58 passes a relatively low frequency (e.g., 0 to 1.5 MHz), but suppresses the amplitude-to-frequency response characteristic to block with relatively high frequency color information contained in the output from the sample hold detector amplifier 54. It has The vertical details are combined in the matrix 42 with the comb-filtered luminance information supplied from the sample hold detection amplifier 54 and the low pass filter 40.

The luminance signal including the comb-filtered and vertical detail information is supplied to the luminance signal processing circuit 64 in the normal form via the common basic transistor amplifier 60 and the coupling capacitor 62. The amplified and appropriately gain controlled luminance signal is supplied from the processing circuit 64 to the matrix circuit 66 and synthesized with the extracted color signal as described below.

A second output from the sample hold detection amplifier 54 passes through the terminal 68 and is supplied to a band pass filter 70 configured to pass a color signal component but block frequencies outside the color signal band. The comb-filtered color signal component is supplied to the color signal processing circuit 76 of a known type through the filter 70. The color signal processing circuit 76 is also supplied with a color burst gate signal as known by the synchronous separator 78 and burst gate generator 80 coupled to the television signal processing circuit 10.

The color signal processing circuit 76 includes, for example, a conventional color subcarrier oscillator (not shown) which is synchronized by a synchronization burst included in the received synthesized signal. The color subcarrier oscillation signal and the comb-filtered color signal component are properly mixed in the color signal processing circuit 76, and a desired color difference signal (e.g., R-Y, G-Y, B-Y) is generated.

Also, the color subcarrier oscillation signal (typically 3.58 MHz in a receiver operating in a standard manner in the United States) is a color subcarrier multiplication (triple) circuit 72 contained in the signal processing device 16 from the terminal 82. Also supplied. The color subcarrier multiplication circuit 72 is, for example, in the form of a phase locked loop and has an output signal having a fundamental frequency (3) times the frequency of a relatively accurate and stable subcarrier oscillation signal supplied from the color signal processing circuit 76. It is prepared to generate. The output from the multiplier 72 is supplied to a logic and clock driver circuit 84 configured to generate correctly timing " strobe " pulses and clock pulses.

₁및

₂는 반대위상으로 50%의 듀티싸이클을 가진 거의 구형파이고, 편의상 10. 7MHz의 클럭신호(그 주파수는 정확하게 3×3. 579545MHz 즉, 이상적인 회로에서는 10. 738635MHz)로 칭해진다. 이들의 클럭신호는 지연선형태의 전하전송장치의 단 사이에서 전하를 전송하기위한 신호로서 적절한 것이다.Clock signal

₁ and

₂ is an almost spherical pie with 50% duty cycle in the opposite phase, and is conveniently called a 10.7 MHz clock signal (the frequency is exactly 3 x 3.579545 MHz, or 10.738635 MHz in an ideal circuit). These clock signals are suitable as signals for transferring charges between stages of charge transfer devices in the form of delay lines.

In the illustrated embodiment of the present invention, each of the delay lines 23, 32, and 50 is in the form of a charge coupling device (CCD) of a general type from the charge transfer device and is also suitable in the form of an embedded channel. . Since a two-phase gate electrode structure suitable for use is of a type constructed using polysilicon material in two levels of gate insulated and isolated, it is described in US Patent Application No. 758,184 filed January 10, 1977. It is of the type described. Moreover, such a device is constructed using the technique of "fill and spill" which transfers charge to the input well of each delay line described in the above-mentioned US patent application. The basis is described in the specification of US Pat. No. 3,986,198 to Mr. Kosonoki. For information other than Mr. Kosonoki's description of the construction and operation of the charge transfer delay line, see Seaqueen and Tomsett, published in 1975 by Academic Press Inc. of New York, New York. It is also described in the commentary of ". A circuit suitable for withdrawing the output signal from the delay line is also described in this manual. A particularly effective configuration described here is a floating diffusion output amplifier.

The delay lines 26, 32, and 50 are also preferably constructed using the techniques for charge transfer and signal introduction described in the specification of US Patent Application No. 708,397 filed in the United States on July 26, 1976. Do.

₁,

₂에 응답하여 연속하는 각단에 신호를 대표하는 전하를 차례로 전송하는 데 있어서, 각 지연선의 제1신호 우물에 전하의 각 다발(packet)을 최초로 전송하는 시간을 적당히 결정할 필요가 있다, 이 일련의 동작을 정확히 타이밍하기 위해 논리 및 클럭구동회로(84)가 설치되어 있어, 클럭신호와 시간관계를 가진 스트로브 즉, 펄스신호 LS₁, SS₁을 발생하여 이들이 신호를 각각 긴지연선(32) 및 짧은 지연선(26) 및 (50)에 공급한다.Clock signal

₁ ,

In order to sequentially transfer charges representing signals to successive stages in response to ₂ , it is necessary to properly determine the time of first transfer of each bundle of charges to the first signal well of each delay line. In order to precisely time the operation, logic and clock driving circuits 84 are provided to generate strobes having a time relationship with the clock signal, that is, pulse signals LS ₁ and SS ₁ so that the signals are long and short delay lines 32 and short, respectively. Supply to delay lines 26 and 50.

In the illustrated embodiment, the short delay lines 26 and 50 have the same number of stages N, and the long delay line 32 is shown as having the larger number N + 682 and half stage. It is. The operation of the device is described assuming that the number of N is one. The difference in delay amount between the long delay line 32 and each of the short delay lines 26 and 50 is determined by the clock frequency (3.579545 x 3 MHz), and the difference in the number of stages is 682 and 1/2. .

Therefore, in the embodiment, the difference in delay amount between the long delay line 32 and the short delay lines 26 and 50 is 682.5 / 3 x 3.579545, that is, 63,555 Hz (1H delay). The reason why a half-level delay is required on one side of the delay line is because the clock frequency is selected as described above. The reason for selecting a frequency three times the color carrier frequency is firstly to meet the Nyquist criterion for sampling data, which requires that the sampling rate be at least twice the highest frequency to be sampled. This is because the clock generation circuit generates the clock signal with the necessary stability without being unduly complicated. The color carrier frequency itself is an odd multiple of one-half the prescan frequency (i.e. fsc = fH x 455/2). Therefore, the clock frequency is also proportional to the prescan frequency.

₁,

₂가 인출된다. 클럭신호로 부터 전하프 리셋트펄스 LS₁,SS₁이 생성되고, 긴 지연선(32)와 짧은 지연선(26) 및 (50)의 입력원 확산전극 즉, S₁전극 (도시안됨)에 각각 공급된다. 이들 전하프티셋트펄스는 클럭펄스와 협동하여 지연선중에 있어서의 전하의 소정의 초기전송을 행한다. 이들 동작은 앞서 지적한 미합중국 특허 제3,986,198호 명세서, 미합중국 특허원 제708,397호 명세서에 기재되어 있는 바와 같다. 긴 지연선(32)에 공급되는 펄스 LS₁은 각각 "온"되기에 앞서 즉,

₁클럭파형의 전하전송의 반싸이클에 앞서, 전하가 주입되도록 타이밍되어 있다. 짧은 지연선(26) 및 (50)에 공급된 펄스(SS₁)은 각각 "온"되기에 앞서, 즉,

₂클럭파형의 전하전송의 반싸이클에 앞서 전하가 주입되도록 타이밍되어있다.The operation of the apparatus shown next will be described. A subcarrier oscillator (usually a crystal controlled oscillator) provided in the chroma signal processing circuit 76 supplies a desired 3.58 MHz subcarrier signal to the color subcarrier multiplier 72 via a terminal 82. Clock waveform of 10.7 MHz from multiplied subcarrier in logic and clock driver circuit 84

₁ ,

₂ is withdrawn. The charge reset pulses LS ₁ , SS ₁ are generated from the clock signal and applied to the input source diffusion electrodes of the long delay lines 32 and the short delay lines 26 and 50, that is, the S ₁ electrode (not shown). Each is supplied. These charge preset pulses cooperate with clock pulses to perform predetermined initial transfer of charges in the delay line. These operations are as described in the specification of US Pat. No. 3,986,198 and US Pat. No. 708,397, as noted above. The pulses LS ₁ supplied to the long delay line 32 are each prior to being " on "

Prior to the half cycle of charge transfer of _one clock waveform, the timing is such that charge is injected. The pulses SS ₁ supplied to the short delay lines 26 and 50 are each prior to being " on "

_The timing is such that charge is injected before the half cycle of charge transfer of the _two clock waveforms.

₁, 우측으로

₂로 도시되어 있는데 대하여, 짧은 지연선(26) 및 (50)에 공급되는 클럭신호는 좌측으로

₂, 우측으로

₁로 도시되어있다. 이것은 긴 지연선 (32)에서는

₁클럭파형이 각 전하전송단의 처음 반분에 공급되는데 대해,

₂클럭파형의 각단의 후반의 반분에 공급되는 것을 도해적으로 표시한 것이다. 긴 지연선 및 짧은 지연선의 입력에 있어서 영상신호를 샘플링하는 샘플링법과 서로 다른 것은 지연선의 한쪽(32)이 1/2단을 포함하고 있다는 것이다. 이 1/2단을 가지는 것은 앞서 설명된 바와 같이 클럭주파수를 특히 색부반송파 주파수의 3배로 선택하는데 관계가 있다. 이경우, 1/2단은 1H의 지연차를 부여하기 위해 필요하다. 지연선의 한쪽이 1/2단을 포함하고 있는 것과, 긴 지연선과 짧은 지연선의 사실상 반대의 시간적 순서로서 클러고디는 것과의 조합에 의해, 같은전하전송의 반싸이클(예를들면,

₂클럭파형의 전하전송의 반 싸이클) 사이에 지연선 26,32,50의 각각으로 부터 전하를 전송할 수가 있다. 따라서, 각 가산회로(28),(52)의 각각에 공급되는 2개의 입력신호는 시간적으로 일치하고 있다.In the figure, the clock signal supplied to the long delay line 32 is shifted to the left.

₁ , to the right

_{Although shown} as ₂ , the clock signals supplied to the short delay lines 26 and 50 are shifted to the left.

₂ , right

_{It is shown as 1} . This is a long delay line 32

₁ clock waveform is supplied to the first half of each charge transfer stage,

_It is shown graphically that what is supplied to the second half of each stage of the _two clock waveforms. The difference from the sampling method for sampling the video signal in the input of the long delay line and the short delay line is that one side 32 of the delay line includes 1/2 stage. Having this half stage is related to selecting the clock frequency, in particular three times the color carrier frequency, as described above. In this case, 1/2 stage is necessary to give a delay difference of 1H. By combining one side of the delay line with one half of the delay line and clumping them in a substantially opposite temporal sequence between the long delay line and the short delay line, a half cycle of the same charge transfer (e.g.,

Charge can be transferred from each of the delay lines 26, 32, and 50 between half cycles of charge transfer of _two clock waveforms. Therefore, the two input signals supplied to each of the addition circuits 28 and 52 coincide in time.

Each terminal G ₁ of the delay lines 26, 32, and 50 includes a luminance signal of full bandwidth (including minute portion information near 4 MHz) and a luminance signal in a frequency band of about 2 MHz to 4 MHz. Interleaved color signals of full bandwidth are supplied. The attenuators 24, 30 and inverting attenuators 48 are configured to have a relatively wide bandwidth suitable for these signals so as not to make substantial changes to each of the above signals. In order to clamp the peak value of the periodic signal of the video signal to a predetermined level to maintain the dynamic operating range of each end of the delay line and the circuits associated therewith, the wideband signal combining circuit in the signal processing device 16 is a conventional direct current reproduction device ( Not shown). The inverter 48 is configured to give a delay slightly different from the delay amounts of the attenuators 24 and 30. Using an N-MOS amplifier that is easy to configure in an integrated form, such a difference in delay amount is kept below 5 nsec, and its value is sufficiently small compared to 1H (63.555 µsec), and the synthesis of color signals entails degradation of quality. I knew it was done without.

Each output of the delay lines 26, 32, and 50 is a sampled data signal that is switched between the reference level and the level representing the video signal at the clock frequency. These sampled data signals include clock frequency components (and their harmonics), baseband signal components and video signal components representing video, and clock frequency components and sideband components distributed above and below the harmonics. .

The sampled Deira signal from the short delay line 26 and the long delay line 32 representing the image information from two sets of continuous lines is added in the addition circuit 28.

Non-interlaced frequency components (e.g., luminance components) are augmented with each other, and interlaced frequency components (e.g., color components) have polarities that cancel each other out. The addition circuit 28 needs to have a bandwidth larger than the range of the luminance / color signal so that the delay amount is accurately matched, and therefore the comb-filtered luminance including the clock frequency and the extra high frequency components distributed up and down at its output. Generate a signal. These high frequency components are removed from the filter circuit 40. In the output of the comb filter 18, the degree of cancellation of the interlace component is mainly due to the difference in the delay amount 1H between the two lines 20 and 22 from the common input terminal 14 to the addition circuit 28. It is determined by the exact degree.

As described above, the two lines are made substantially the same except for the difference between the number of CCD transmission stages (i.e., 682 and 1/2 stages), so the difference in delay amount is determined by the difference in the number of stages and the frequency of the clock signal. The singular is fixed by the physical structure. In addition, the clock frequency is determined by the frequency of the color carrier oscillator. The color carrier frequency is extremely accurate and is itself locked to an interlaced color burst component with a received color signal. Therefore, the delay amount difference between the two lines is accurately set and maintained by the subcarrier frequency. Among the two signal paths of the luminance signal comb filter 18 including the addition circuit 28 and reaching the addition circuit 28, frequency selective concentration affects the phase or amplitude response of any line in the luminance signal or color signal frequency domain. The water filter element is not included at all. In order to remove the clock signal and its sideband components, the low pass filter 40 associated with the luminance signal comb filter 18 is located outside the comb filter itself and is provided behind the addition circuit 28. Therefore, the filter 40 does not have a bad influence on the delay time and amplitude characteristics of the luminance signal comb filter 18. The filter 40 need not match the filter characteristics associated with other circuitry in the device. It is not necessary to provide adjustable delay means in any of the long delay line with the delay line 32 and the short delay line with the delay line 26. A separate delay device 34 capable of using two-stage CCD lines with a delay time of 186 nsec substantially (each end of each line receiving a delay of 93 nsec when clocked at 10.7 MHz) is dependent on the comb filter 18. As described later, it has the effect of equalizing the delay of the comb-filtered signal associated with the vertical detail luminance component passing through the low pass filter 58 in a relatively narrow band.

At the output of the addition circuit 28, the degree of cancellation of the interlaced signal components depends on the relative attenuation of each of the long and short delay paths, i.e. gain. Since the charge transfer efficiency of the buried channel type CCD is sufficiently high, the attenuation of the long delay line and the short delay line is very precisely matched. Thereby, in each comb filter, the ratio of a required frequency component and an unnecessary component can be set to about 30 db. If it is necessary to deepen the nodes of the synthesized signal, a suitable DC control gain adjusting device may be used in each signal path (e.g., the attenuator 24, 30 of the same type as the inverting attenuator 48). In the middle). This "trimming" circuit needs to have the desired wide bandwidth so as not to adversely affect the exact delay difference of 1H.

In the comb-type filtered luminance signal output of the addition circuit 28, the chroma signal component is not substantially included. In a typical television signal processing apparatus which does not limit the high frequency portion of the luminance signal and does not perform a comb-shaped filter, "dot-crawl" gradually moving along a large color region or vertical edge appears, but is produced by the apparatus of the present invention. Such " dot-crawl " does not occur at all in the image reproduced by the luminance signal. Furthermore, at the output of the addition circuit 28, high frequency luminance information (near 2 MHz to 4 MHz) becomes augmented, i.e., peak, without accompanying such unfavorable color " dot-craw " disturbing effect.

The data signals sampled from the long delay line 32 and the short delay line 50 (inverted images are supplied to the latter short delay line) are added to each other in the broadband addition circuit 52. The non-interlaced frequency components supplied by the delay lines 32 and 50, for example, the luminance signal components gathered around harmonics of the prescan frequency, are provided with an inverting attenuator 48 in one delay line 46. It is subtracted from each other by being. These non-interlace components supplied from the continuous lines cancel out in the addition circuit 52. The remaining signal components appearing at the output of the addition circuit 52 include the interlaced color signal components and the vertical detail information existing between the harmonics of the line frequency in the range of 0 to 1 MHz. Furthermore, a clock frequency component and a sideband wave centered on this frequency component exist at the output of the addition circuit 52 having the same shape as the comb filter 18 for the luminance signal.

A regional pass filter 58 is provided to separate low frequency vertical detail information (and signals related to the remaining clock frequency) from the color signal components. The bandpass filter 70 selects color information to remove a signal related to one vertical detail signal and a clock frequency. It goes without saying that the filters 58 and 70 do not affect the comb filter of the delay lines 32 and 50. The low pass filter 58 has a narrower frequency response than the low pass filter 40 associated with the main comb filter output. The delay line 34 is provided for delaying the main luminance signal after the comb filter so that two inputs are simultaneously supplied to the matrix 42.

Therefore, the low frequency vertical details are added to the remainder of the luminance signal information which is moderately delayed in the matrix 42. When it is desirable to select the degree or peak of the vertical detail included in the luminance signal generated at the output of the matrix 42, the variable attenuation and amplifying stages may be provided in the matrix 42. The overall luminance signal is supplied to the luminance processing circuit 64 in a conventional manner, and finally to the display. The luminance signal generated in this way contains a frequency component substantially higher than that typically seen in commercially available television receivers (for example, in the range of 3 to 4 MHz). Therefore, the luminance signal processing stage needs to have sufficient bandwidth to display an image having a desired high luminance resolution.

The comb-filtered color signal having the full bandwidth generated at the output of the filter 70 is processed by the color signal processing circuit 16 in a conventional manner, and the mixed color generated when the luminance signal information is present in the color channel near the color carrier frequency (cross) Color difference signal with little disturbance can be generated. The matrix 66 generates three new signals R, G, and B for supplying the display device with a combination of relatively unobstructed luminance signals.

Although the sample hold amplifiers 36 and 54 shown are not essential to the operation of the present invention, the clock frequency components in these signals are attenuated before transmitting signals from the terminals 38, 56, 68. It has an effect. Moreover, this sample hold amplifier (sampled with a clock frequency wave with 50% duty cycle as described above) has the effect of doubling the level of the output video signal compared to a low pass filter with a simple passive element. The sample hold amplifiers 36 and 54 are controlled in a normal operation form by sampling pulses drawn from the clock wave.

Although the present invention has been described with respect to a configuration suitable for processing NTSC-type color television signals in a color television receiver, the present invention is generally based on the present invention in terms of signal processing. Apparently, the present invention can also be applied to processing color television signals formed according to a separate standard method used in a reproducing apparatus or a transmitting apparatus.

In addition, various modifications may be made to the apparatus of the embodiment without departing from the scope of the present invention. For example, in one or more signal paths of the signal path having delay lines 26, 32, and 50, a broadband gain control or attenuating device may be provided before or after the delay line. By adjusting such an amplitude control device to control the relative amplitude of the signal in each signal path, it is possible to improve the angular effects such as the enhancement of the transmission of the frequency component which requires the removal of unsuitable frequency components. A variable gain amplifier may be provided in or before the matrix circuit 42 to adjust the amplitude (vertical peak) of the vertical detail signal or to selectively amplify any frequency component of the comb-filtered luminance signal. In any case, since the comb filter is performed before the control such as adjustment and amplification, the variable gain amplifier does not affect the comb filter action of the apparatus. It goes without saying that other modifications may be considered within the scope of the present invention in addition to these modifications.

Claims (1)

Apparatus for supplying an input signal comprising at least a first information component and at least a portion of a frequency spectrum of the information component comprising signal energy concentrated in each vicinity of a plurality of frequencies spaced by a frequency equal to the first frequency ( 10); An apparatus (84) for supplying a timing signal of a frequency proportional to said first frequency; At least first and second signal processing lines (26 and 32) each having an input coupled to the input signal supply (10) and an output of a delayed signal; An apparatus (28) for synthesizing the output signals from the first and second lines to generate a composite signal having a comb-like frequency spectrum having a maximum point at a position separated by a first frequency; In the electric signal processing device having a filter device 40 coupled to the signal synthesizing device 28 and passing a frequency band including a frequency related to the first information component, the first line 26 and the second line. The line 32 has a different number of signal delay stages for transmitting a signal representing an input signal between an input unit and an output unit in response to the timing signal, and the first line and the second line have a frequency of the timing signal. And an delay time difference with respect to an input signal which is inversely proportional to and proportional to the difference in the number of stages in the line.

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