JPS62113283A - Absolute value circuit - Google Patents

Abstract

PURPOSE:To improve temperature characteristics by providing an adder which adds the 1st and the 2nd difference currents together and generates a sum output current and a current-voltage converter which converts the sum output current into an output voltage. CONSTITUTION:The 1st and the 2nd mutually opposite-phase currents outputted by a differential current converter 6 are supplied to the 1st and the 2nd difference current detecting circuits 8 and 11 and converted into the 1st and the 2nd difference currents there. Those 1st and 2nd difference currents have the same polarity and are outputted alternately by the 1st and the 2nd difference current detecting circuits 8 and 11 in mutually different periods. The 1st and the 2nd difference currents are summed up by the adder 13 and then converted by the current-voltage converter 14 into an output voltage, thus obtaining the output voltage which is equal in absolute value to an input voltage. Thus, detection precision and stability to temperature variation are improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an absolute value circuit, and more particularly, to an absolute value circuit that generates an absolute value voltage of an input voltage.

2. Description of the Related Art Conventionally, absolute value circuits have been used in various signal processing fields as signal amplitude detectors necessary for, for example, automatic gain a/Itl11 circuits.

FIG. 11 shows a circuit diagram of an example of a conventional absolute value circuit. During rotation, 1 is the input terminal, 2 is the NPN transistor Qa,
A well-known differential amplifier consisting of a current source Qb, a current source (a), a reference voltage source that generates a reference voltage V, and resistors Ra to Rd is not shown. Further, 3 indicates a signal selection circuit consisting of NPN transistors Qc and Qd and a current jffl Ib commonly connected to their emitters, and the connection point of the emitters is connected to the output terminal 4.

Here, when an input voltage va that changes as shown in FIG. The voltage Vb changes as shown in FIG. 12<8) and (C).

Vc is output from the collectors J of transistors Qa and Qb. However, the above V' is a polymorphism of the collector voltage of the transistors Qa and Qb, which is Va-V.

The voltages vtt and vc are the transistors Qc and Qd.
supplied to each base. As is well known, the signal selection circuit 3 outputs the larger of the input voltages Vb and Vc to the output terminal 4.

Here, the difference between the input voltage Va and the reference voltage V is ΔVa
(=Va-V), the above types JIVb and VC are expressed as equations (1) and (2), respectively.

vb=v'-ΔVa (1) VC
=V' +Δva ■Therefore, the voltage Vd output to the output terminal 4 is
If the forward direction base-emitter voltage of d is set to VIII, it can be expressed as in equation 0.

Vd=lΔVa l+V' −VIE (3
) In this way, the output voltage v4 becomes such that the absolute value of the voltage difference 1ΔVa l is added to the reference voltage (V' - V8 E ), as shown in FIG. 12(D). It becomes a waveform. Therefore, the circuit shown in FIG. 11 has an input voltage of
It operates as a so-called absolute value circuit in which the absolute value of a is output as the output voltage Vd.

Problems to be Solved by the Invention However, the signal selection circuit 3 has an output voltage Vd divided by the output impedance of the transistors Qc and Qd, so that the voltage difference between its inputs is small.
For example, if l Vb - Vc l < 100 IIV), the linearity of the output will change as is well known.

Therefore, the conventional absolute value circuit described above has the disadvantage that its absolute value output has non-linear characteristics when a small signal is input.

Furthermore, in the conventional absolute value circuit described above, its output voltage V
The reference voltage V'-VIE of d is a fixed voltage value,
Since this cannot be set freely, there is a problem in that the t & continuation conditions of the circuit subsequent to the absolute value circuit are limited to Hi11. Furthermore, the above reference Ti pressure is VI
There are problems such as the temperature characteristic associated with E and the need to compensate for this temperature characteristic in a subsequent circuit.

Therefore, the present invention converts the absolute value circuit into a differential current converter, the first
It is an object of the present invention to provide an absolute value circuit that solves the above problems by comprising a second differential current detection circuit, an adder, and a current-voltage converter.

Means for Solving the Problems (1) The absolute value circuit according to the present invention includes a differential current converter that generates and outputs first and second currents having opposite phases according to an input voltage, and a differential a first difference current detection circuit that selects one of the difference currents between the first current from the current converter and a preset reference/upstream current and outputs it as a first difference current; a second difference current detection circuit that selects one polarity of the difference current between the second current from the converter and the reference current and outputs it as a second difference current; It is composed of a converter that generates an additional output current by adding an additional current, and a current-voltage converter that converts the added output current into an output voltage.

The first and second currents of opposite phase output from the wearable differential current converter are supplied to first and second difference current detection circuits, where the first and second difference currents are is converted to The first and second difference currents both have the same polarity, and are output in alternating η in different periods from the first and second difference current detection circuits.

After the above-mentioned first and second difference currents are summed by a pumping device,
It is converted into an output voltage by a current-to-voltage converter. In this way, an output voltage that is the absolute value of the input voltage is obtained.

Next, an embodiment of the circuit of the present invention will be described with reference to FIGS. 1 to 10.

Embodiment FIG. 1 shows a block system diagram of a first embodiment of an absolute value circuit according to the present invention. In the figure, the input voltage V1 input to the input terminal 5 is supplied to the differential current converter 6, where a current of an opposite phase is generated according to the difference from a predetermined reference DC voltage VB, which will be described later. 11 and I2. This current I+ is supplied to a current comparator 39 which together with the base 111 and the current source 7, which generates and outputs the reference current IO, constitutes a differential current detection circuit 8.Similarly, the L open current I2 is , (is supplied to a core number comparator 12 which constitutes a difference current detection circuit 11 together with a reference current source 10 that generates and outputs a quasi-lightning current 1o.

Current comparison i! ! i9 is the incoming current 11 and the reference current ro
In the period in which the current 11 is smaller than the base*current IO, the difference current 13 between the two (i.e., l3
= IQ It and 13>O) and outputs it to the adder 13. Similarly, current comparator 12
are the incoming current I2 and the reference current I. In the period when the current I2 is smaller than the reference current 1o, the difference current 14 between the two (i.e., Ia=Io 12,
and 14 > 0) is generated and output to the adder 13.

Adder 13 adds incoming currents I3 and I4, respectively.
4F4jcTi'a I s (-[3+ It >
0) Output to the current-voltage converter (1-V converter) 14.

The l--2 converter 14 converts the incoming current 15 into an output voltage (2) and outputs it to the output terminal 15. In this way, an output voltage V2 proportional to the absolute value of the input voltage V+ is obtained.

FIG. 2 shows a specific circuit system diagram of the block system shown in FIG. 1. In the same figure, the same components as those in FIG. Here, l electrodynamic number converter 6 is NPN
+- transistor Q1. Q2, a current +11i16.17 that generates and outputs a reference current 1o, a reference DC voltage source 18 that generates and outputs a reference DC voltage V's, and a resistor R+.

Here, the transistor Q1 has its base connected to the input terminal 5, and its emitter connected to the current source 1.
6 to ground. On the other hand, - the transistor Q2
Its base is grounded via a reference DC voltage source 18, and its emitter is grounded via a current source 17. Further, both emitters of transistors Q1 and Q2 are connected through respective resistors R1.

The differential current detection circuit 8 includes an NPN transistor Q3,
It is composed of a PNP transistor Q4 and the reference current source 7, while the difference current detection circuit 11 is composed of an NPN transistor Qs, a PNP transistor Q6, and the reference current source 10.

Here, a reference current source 7 is connected between the collector and emitter of the transistor Q3, and its emitter is connected to one terminal of the transistor Q4. A common connection point between the 1-bit transistors of the 1-transistors Q3 and Q4 and the reference current source 7 is connected to the collector of the transistor Q1.

On the other hand, a reference current source 10 is connected between the collector and emitter of the transistor Q5, and its emitter is connected to the one-way terminal of the transistor Q6. ] - transistor Qs, emitter of Qs people and reference current m10
A common connection point of is connected to the collector of the transistor Q2.

Also, the collector of transistor Q3 is connected to transistor Q3.
! The base of the transistor Q3 is connected to the transistor Q5 and the anode of the diode D2.
and the connection point between the cathode of the diode D2 and the anode of the diode D1, respectively. On the other hand, the base of the 1-transistor Q4 is connected to the base of the 1-transistor Q6, the cathode of the diode D1, and the connection point of one current source. Further, the power supply terminal supplying the power supply voltage +VCC is grounded through diodes D2 and D+ and a current source 19 in series.

Thus, between the respective collector bases of transistors Q3 and QS, and between the base of transistor Q3 and QS and transistor Q4. The bases of Q6 are biased by diodes D+, D2 and current sources, respectively.
This prevents saturation of transistors 03-Q6.

On the other hand, the adder 13 is simply a junction of the collectors of transistors Q4 and Q6. Further, the 1-V converter 14 has a resistor R2 and a DC voltage V. It is composed of a DC voltage source 20 that generates and outputs. Here, the above-mentioned node is connected to the output terminal 15, and is also grounded through the resistor R2 and the DC voltage source 20 in series.

Next, the operation of the circuit system shown in FIG. 2 will be explained with reference to the signal waveform diagram shown in FIG. Now, as shown in FIG. 3(A), the input 'ilf ITV + coming into the input terminal 5 is expressed as V+=Vn (-ΔV and J, as is well known, respectively of the transistors Q1 and Q2). Figure 3 (B
) and (C), and differential currents 11 and I2 are generated as shown in equations (4) and 6).

1+=Io+ΔI(4) [2=Io−Δl ■On the other hand, the emitters of transistors Q3 and Q4, m1lT! 7 and the collectors of the transistor Q1 are connected in common, so a difference current 11-1°=Δl is generated at the emitters of the transistors Q3 and Q4, respectively. In this case, the current 1
Corresponding to the polarity of 1, one of the transistors Q3 and Q4 is turned on, and the other is turned off. That is, time t
As shown in 1 to t2 and t3 to t4, (+ −!0≧0
When , transistor Q3 is turned on, and transistors 1 to Q4 are turned off. Moreover, as shown in time t2 to [3,
When I+ -1o <Q, transistor Q3 is turned off and transistor 04 is turned on. Therefore, the period during which the transistor Q4 is on (from time 12 to
Only during the period indicated by t3, etc., a differential current I3 as shown in FIG. 3(D) is generated from the collector J of the transistor Q4.

Similarly to the above, a difference current 12 1o=-ΔI is generated in the emitters of transistors Q5 and Q6, respectively, and in this case, corresponding to the polarity of current [2, transistors Q3 and Q4
One of them is turned on and the other one is turned off.

That is, as shown at times t1 to t2 and t3 to t4, <1
2 When 1o<O, transistor Q5 is turned off,
1- transistor Q6 is turned on. In addition, as shown from time t2 to time t3, when <12 1o≧O, ]-transistor Q
s is turned on and transistor 06 is turned off. Follow,
Therefore, only during the period when transistor Q1 to Q6 are on ('!j, that is, the period shown from time 1+ to t2 and from t3 to t4, etc.), the voltage from the collector of transistor Q6 as shown in FIG.
A differential current 14 as shown in E) is output.

The above-mentioned difference currents I3 and I4 are expressed by the following equations (6) and (6), respectively.

13=IO[+ (6
)14 =IO-12(i') In this way, when the voltage Δ■ is Δv>0, the difference current 14
is output, the difference current becomes zero, and when Δ■ is O, the difference current 13 is output, and the difference current 14 becomes zero, and as the voltage ΔV becomes positive Ω, the difference currents 13 and 14 alternate with the adder 13. is output to.

The adder c'i device 13 adds up the incoming differential currents 13 and I4, respectively, and generates a current 5 as shown in FIG. 3(F).
-Output to V converter 14. This current r5 is expressed as in equation (8), where Is=13+IJ=lΔIle.In the end, the current is proportional to the absolute value of the voltage ΔV.

By the way, the conversion gain P of the differential current converter 6 is expressed as P=1/r+ when the resistance value of the resistor R1 is 1, and between the voltage Δ■ and the current ΔI, ΔI= Since there is a relationship of P and ΔV, the above equation 0 can be rewritten as equation 0).

I5= (1/rt) ・lΔV1 0) Next,
1-V converter 1/I converter (qq is expressed as Q=r2 when the resistance value of resistor R2 is divided by r2. Therefore, I-V
Output voltage v2 output from the converter 14 to the output terminal 15
is expressed as equation (10), V2 = Vo +Q Is = Vo + (r2/r+
)・1ΔV I (10) The waveform becomes as shown in FIG. t3 (G). In this way, the circuit system shown in FIG. 2 has a conversion gain of r 2 / r
+, it operates as an absolute value circuit in which the absolute value voltage of the input voltage v1 whose reference voltage is Vo is 19. In this case, the reference voltage ■. and resistance value rl.

By changing r2, the absolute value output level can be easily and freely set.

FIG. 4 shows a circuit system diagram of a second embodiment of the circuit of the present invention.

In the figure, the same components as in FIGS. 1 and 2 are denoted by the same reference numerals, and the numerals ``A'' and ``A'' are omitted as appropriate. This second example is characterized in that the polarities of the currents 13 to I5 in the first example are reversed. '? J <z
That is, in FIG. 4, the collectors of transistors Q4 and Q6 are grounded, and the collectors of transistors Q3 and Q6 are still grounded.
common emitter connection point of J and transistors Qb, Qs
The jt emitter connection point of is connected to the power supply terminal via reference current sources 7 and 10, respectively, and the collectors of transistors Q3 and Qs are connected, respectively, and this node constitutes the adder 13. In addition, as will be explained later, in conjunction with the newly provided diode D4, a diode D3 is newly inserted and connected between the power supply terminal and the anode of the diode D2, and thereby the transistor Q3. Setting the base bias of Qs to prevent its saturation,
This makes it easy to connect later stages.

With the above configuration, the polarity is different from that of the first embodiment, and
Difference current 1'311'4 as shown in Fig. 3 (E) and (D)
is output from the collectors of transistors Q3 and Qs,
Further, a current I5 as shown in FIG. 3(F) is outputted from the adder 13. On the other hand, kV variable 1fii5ii shown in Fig. 4
14 is a diode D4 and a PNPt-transistor Q7
A well-known current mirror circuit consisting of the resistor R2 and the resistor R2
1 DC'I! The connection point between the base of the i-transistor Q7 and the cathode of the diode D4 is connected to the adder 13, and the connection point between the base of the i-transistor Q7 and the cathode of the diode D4 is connected to the
The collector of is connected to the output terminal 21 and the resistor R
2 and a DC voltage source 20 in series.

Here, if the current amplification gain of the current mirror circuit is n, the output M current 1's output from the collector of the transistor Q7 becomes Bi5 = n-l5, so the second
The conversion gain q' of the r-v'a converter 14 according to the embodiment is q'
=nr2. Therefore, the output voltage V2' output to the output terminal 21 is expressed as equation (11).

V2' = Vo +n・(r2/r+)・1ΔV l
(11) In this way, the circuit system shown in FIG. The second embodiment has the advantage that the conversion gain can be increased by 6 compared to the first embodiment, and the maximum value of the output voltage V2' can be increased to approximately the power supply voltage VCC. are doing.

In addition, in the circuit system shown in FIG.
, QJ are commonly connected to the connection point of the diode D1 and the current source 19 as shown in FIG. , Qs) may be configured to be set to zero bias.

Similarly, in the circuit system shown in FIG. 4, the bases of transistors Qx and QJ are commonly connected to the connection point of diode D1 and current source 19 as shown in FIG. The base-to-base bias of QJ (and transistors Qb and Qs not shown in FIG. 6) may be set to zero bias.

Figure 7 shows a circuit system diagram of the third embodiment of the circuit of the present invention-4
In the drawings, the same components as those in FIGS. The feature is that the bias diodes DI to D3 and the current source 19 are not required.Here, the difference current detection circuit 8 is a current mirror circuit consisting of a diode O5 and a PNP transistor Q8, and a level shifter 1-. Diode D61 return 1
-Ran resistor Q9. Clamp transistor Q+a and M
If 1, (applicable flow FA7 J:
A current mirror circuit consisting of a transistor Qn, a level shift diode Da, a feedback transistor Q12. The clamp transistor Q13 and the V quasi current source 10J are configured. Since the configurations of the differential current detection circuits 8 and 11 are the same, the following description will mainly take the differential current detection circuit 8 as an example.

The anode and cathode of a diode D5 are connected between the emitter and base of the transistor Q8, respectively, and the connection point between the base of the transistor Q8 and the cathode of the diode D5 is connected to the collector of the transistor Q1 via the level shifter 1 to the diode D6. Ru. Further, the base of the 1-transistor Q8 is connected to the emitter of a feedback transistor Q9, and the base of this feedback transistor Q9 is connected to the collector of the transistor Q8, the emitter of the clamp transistor Q+o, and the (l) of the base Q current source 7 whose one end is grounded.
! Each is connected to IE. Further, the collector of the clamp transistor QIO is grounded, and the base thereof is connected to the connection point between the cathode of the level shift diode D6 and the collector of the transistor Q1.

The anodes of the diodes Ds and D7 and the emitters of the transistors Qa and Qu are respectively connected to a power supply terminal, while the collectors of the feedback transistors Q9IQ+2 are commonly connected, and the adder 13 is constituted by the node thereof.

Next, to explain the operation of the third embodiment, as shown at times t2 to t3 in FIG. 3(B), when <It<io, the current 11 flows through the diodes D5 and D6.
Due to the well-known nature of current mirror circuits, the collector current Ic8 of transistor Q8 is equal to Ice-1+. However, the reference current source 7 is connected to the collector of the transistor Q8, and its rA'l' current. is 11 as above
Since the collector potential of transistor Q8 (
That is, the potential (to the common connection point of reference current source 7.1 to the collector of transistor Q8, the base of feedback transistor Q9, and the emitter of clamp transistor Q10) tends to decrease. This change in potential is caused by the feedback transistor Q
The current is fed back to the input end of the current mirror circuit through the base-emitter of the transistor Q9, thereby increasing the current of the diode D5 and increasing the collector current Ice of the transistor Q8. This feedback operation is
This continues until Ice=Io, after which an equilibrium state is reached.

In this case, the current increase in the collector current Ic8 is [o
l+, and a current equal to this current increase is outputted between the diode Ds and the emitter-collector of the transistor Q9. At this time, the clamp transistor Q+o is set to zero bias, which is A).

On the other hand, contrary to the above, in FIG. 3(B), time t1 to t2
When <I+≧L, as shown in t3 to t4, the potential at the common connection point A rises, and the reflamp 1 transistor Q In is turned on. Also, since the feedback resistor Q9 is set to zero bias and is turned off, its collector output current becomes zero.

In this way, a difference current 13 as shown in FIG. 3(D) is output from the collector of the feedback transistor Q9 to the adder 13.

The same operation as above is also performed in the differential current detection circuit 11, and the result is zero when I2≧10, and a level corresponding to the differential current Δ1 only when +2<10, as shown in FIG. 3(E). A difference current 1a (=10 12 - ΔI) is output from the collector of the feedback i transistor Q12 to the adder 13.

The adder 13 adds the incoming differential currents 13 and 14, respectively, to generate a current 5 as shown in FIG. 3(F), and outputs it to the kV converter 14. The I-■ converter 14 performs the same operation as described above, and as a result, the output voltage V2 that satisfies the above equation (10) is outputted to the output terminal 22.

FIG. 8 shows a circuit system diagram of a fourth embodiment of the circuit of the present invention.

In the figure, the same components as in FIG. 7 are designated by the same reference numerals, and their explanations will be omitted. Here, the other end of the current source 7 whose one end is grounded is connected to the connection point between the cathode of the diode D6 and the base of the clamp transistor Q+o, and similarly, the other end of the current source 10 whose one end is grounded is connected to the connection point of the cathode of the diode D6 and the base of the clamp transistor Q+o. It is connected to the cathode of D8 and the connection point between clamp 1 and the base of transistor Q13. Further, the collector of the transistor Q+ is the collector of the transistor Q8.

The =l collector of transistor Q2 is connected to the common connection point of the base of feedback transistor Q9 and the emitter of clamp transistor QIG, and similarly, the =l collector of transistor Q2 is connected to the common connection point of the collector of transistor Qn, the base of feedback transistor Q+2, and the emitter of clamp transistor QI3. Connected to a connection point.

Next, to explain the operation of the circuit system shown in FIG.
Since the configurations of the differential current detection circuits 8 and 11 are the same, a brief explanation will be given below, mainly taking the differential current detection circuit 8 as an example.

Now, when 11≦10, the clamp transistor Q+o
is turned on because its base potential drops, and on the other hand, feedback transistor Q9 is turned off, so that the collector current of feedback transistor Q9 is not output. On the contrary, 1
When 1>Io, the clamp transistor Q+o becomes Aoff because its base potential is sufficiently high, and on the other hand, the feedback transistor Q9 is turned on, so the feedback transistor Q9
A difference current [+Io-ΔI] is output from the collector of . As a result, the differential current ■3 as shown in Fig. 3 (・E)
' is output to the adder 13 from the collector of the feedback transistor Q9.

Similarly to the above, in the differential current detection circuit 11, ■2≦
It becomes zero when Io, and on the other hand, the difference current 1 when 12>10
A difference current 14' having a level of 21o-Δ■ as shown in FIG. 3(D) is outputted to the adder 13 from the collector of the feedback transistor QI2.

In this way, the difference current detection circuit 8.11 in the circuit system shown in FIG. 8 generates a difference current [3', I4' is output. As a result, the voltage V2 is applied to the output terminal 23.
is output.

FIG. 9 shows a circuit system diagram of a fifth embodiment of the circuit of the present invention.

In the figure, the same components as in FIGS. 1 and 2 are denoted by the same reference numerals, and the explanation thereof will be omitted as appropriate. Here, the differential current detection circuit 8 is composed of a current mirror circuit composed of PNP transistors Qn, QCs and a diode D9, a clamp transistor Q+s and the reference current +1127, while the differential current detection circuit 11 is composed of PNP transistors Q+y, QCs. and a current mirror circuit consisting of a diode DIG.

It is composed of a clamp transistor Q+s and the reference current source 10. Since the configurations of the differential current detection circuits 8 and 11 are the same, the following description will mainly take the differential current detection circuit 8 as an example.

The anode and cathode of a diode D9 are connected between the emitter and base of the transistor On, and the emitter and base of a transistor Q+s are connected between the base and collector of the diode D9, and between the emitter and collector of the transistor Q14. A reference current source 7 is connected. A common connection point B between the collector of this transistor Q14, the base of the transistor 015, and the reference current source 7
is the emitter of the clamp transistor QI6 and the
They are respectively connected to the collectors of transistor Q1.

On the other hand, the connection point of the emitter of the transistor Q14, the current source 7, and the anode of the diode D9 is connected to the power supply terminal, and the diodes DI1.
DI2 is grounded via current source 24. Further, the collector of the clamp transistor Q16 is grounded, and its base is connected to the connection point between the cathode of the diode 012 and the current source 24.

In this way, since the clamp transistor Q16 has its base biased by the diode 0111012 and the current source 24, if the forward voltage drop of the diode D11°DI2 is expressed as Vo, then the input terminal (g That is, the voltage at the common connection point B) is Vc
It is clamped to c-Vo, thus preventing the reference current source 7 from saturating.

On the other hand, the collectors of the transistors Q15 and QCs are commonly connected, and the adder 13
is configured.

Next, to explain the operation of the fifth embodiment, when <I+>Io as shown at times tl to t2 and t3 to j: 477 in FIG. 3, the potential at the common connection point B is Therefore, the clamp transistor Q16 is biased to zero and turned off, while the transistors 014 and QCs forming the current mirror circuit are turned on. As a result, the current mirror circuit operates, and a difference current 13' (=I+Io=Δ■) as shown in the third (E) is output from the collector of the transistor Q15.

Also, as shown at times t2 to t3 in FIG. 3, 1+≦
To Nodoki, the above jAm style 13' is Gyakuyang↑! [Then, the current mirror circuit is cut off and the transistor Q+
s]rector output becomes zero. This +Ll,, current I.

flows into the emitter of the clamp transistor Q16, turning it on, and the common connection point B is grounded through the emitters of the clamp 1 to the transistor QI6 and the transistor.

The same operation as above is performed in the differential current detection circuit 11, and the current becomes zero when 12≦Io, and reaches a level corresponding to the current ΔI only when 12>10, as shown in FIG. 3(D). A differential current 14' (=12 10-Δ1) is output from the collector of the 1-transistor Q+a.

Addition? +13 incessantly squeezes the incoming differential currents 13' and I4' to generate a current 15 as shown in FIG. 3(F),
Output to the 1-V converter 14.

iV converter 141. i Do the same 111 works as above,
As a result, the output voltage v2
is output to the output terminal 25.

FIG. 10 shows another difference current detection circuit 8 and 11 in the circuit system shown in FIG. 9 (however, since the difference current detection circuits 8 and 11 have the same configuration, the illustration of the difference current detection circuit 11 is omitted) A circuit diagram of the embodiment is not shown. In the figure, the same components as in FIG. 9 are given the same reference numerals. The circuit system shown in FIG. 10 includes the transistors 1 to Q14. Instead of the current mirror circuit consisting of Q15 and diode D9, P
It is characterized by the provision of a current mirror, a circuit, and a diode DI4 consisting of an NP transistor Qn and a diode DI:1.

In FIG. 10, the anode and cathode of a diode 013 are connected to the emitter base of the transistor Qn, respectively, and the connection point between the pace of the transistor Q20 and the cathode of the diode 013 is connected to the current ? through the diode DH in the forward direction. l! i7° Connected to the connection point between the emitter of the clamp transistor QI6 and the collector of the transistor Q1. Further, the connection point between the emitter of the transistor Q~ and the anode of the diode 013 is connected to the current source 7 and the anode of the diode D11, respectively.

The diode DH sets the base bias of the transistor Q2o, thereby ensuring the on/off operation of the current mirror circuit and the clamp transistor QI6.

In the F configuration, when It≦1o, the clamp transistor Q16 is turned on, and on the other hand, the current mirror circuit is cut off, so the collector output of the transistor (ha) becomes zero.Next, when It>1o, the clamp transistor Q16 is turned on. 1
~ Since the transistor Q16 turns off and the current mirror circuit turns on, the difference current 1+Io flows through the diode 013 and DI4, and as a result, the difference current 13 as shown in FIG. 3(E) flows from the collector of the transistor Q21. '(=I+Io) is output.

Next, the output linearity when a small signal is input in the circuit of the present invention will be explained. Now, the input/J voltage V1 is V+=Vo
If so, the ΔV becomes small, and the difference current ΔI also becomes small. However, the current comparator constituted by the transistor and diode J in the differential current detection circuit 8.11 responds to the polarity of the difference current between its input current 11.12 and the reference current 1° by its output transistor (1) 4. Transistor Q4.
Q6, feedback transistor Q2. QI2 and 1 - transistor QCs.

(corresponding to QCs and Qpa), so regardless of the magnitude of the difference current ΔI, the linearity is maintained at MtI! It is possible to output differential currents 13 and 14 (or 13' and 14'). Therefore, according to the circuit of the present invention, the linearity of the absolute value output is not impaired even when a small signal is input.

Further, since the circuit of the present invention can set the output reference voltage to any voltage completely independent of other circuit operations, the circuit has good temperature characteristics and can obtain a stable absolute value output. Furthermore, the conversion ratio between input and output is 19, and the resistors R1 and R2 are
Since it is determined by the resistance ratio r 2 / r + customer, it can be set independently of the reference voltage, and there are no restrictions on the connection conditions of subsequent circuits.

Note that the differential current detection circuit 8.1 which forms the main part of the circuit of the present invention
It goes without saying that the configuration of No. 1 is not limited to this embodiment, and that various configurations can be obtained by changing the combinations of transistors, diodes, current sources, and the like.

Effects of the Invention As described above, according to the present invention, the absolute value circuit is connected to the differential current 9
converter, first and second differential current detection circuits.

Since it is composed of a booster and a current-voltage converter, it is not affected by the output impedance of transistors, etc., and the absolute value output voltage with good linearity even when a small signal is input is (q). It is possible to realize an absolute value circuit that can uniquely set the reference voltage and arbitrary conversion gain.For example, it can be applied to signal level detection circuits such as automatic gain control circuits.
It has features such as being able to improve detection accuracy and stability against temperature changes.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are respectively the first example of the absolute value circuit according to the present invention.
Block system diagram and circuit system diagram of the embodiment, Fig. 3 (
A) to (G) are signal waveform diagrams for explaining the operation of the circuit of the present invention, FIG. 4 is a circuit system diagram showing a second embodiment of the circuit of the present invention, and FIG.
6 and 6 are circuit system diagrams showing the embodiments of the differential current detection circuits in the circuit systems shown in FIGS. 2 and 4, and FIGS. 10 is a circuit system diagram showing other embodiments of the differential current detection circuit in the circuit system shown in FIG. 9, and FIGS. 11 and 12 are respectively FIG. 2 is a circuit diagram showing an example of a conventional absolute value circuit and a signal waveform diagram for explaining its operation. 5... Input horn terminal, 6... Differential current converter, 7.1
0...Reference current source, 8, 11...Difference current detection circuit,
9゜12...Current comparator, 13...Additional unit, 14.
・・Current-voltage converter, 15.21.22.23.25
...Absolute value voltage output terminal, 16.17.19.24.
... Current source, 18... Reference DC voltage source, 20... Current voltage source, D1 to DI4... Diode, Q1 to Qs
, Qu. Q14. QIs, Q10, 0Cs, Qto
・"I-ransistor, Qs, Q12-feedback transistor, QIO, Q13. QI6IQ+!]...Clamp transistor, R+
, R2...resistance. Patent applicant: Japan Victor Co., Ltd. Seal Figure 2

Claims (1)

[Claims] a differential current converter that generates and outputs first and second currents having opposite phases to each other according to an input voltage; and a difference between the first current from the differential current converter and a preset reference current. a first difference current detection circuit that selects one polarity of the current and outputs it as a first difference current; and one of the difference currents between the second current from the differential current converter and the reference current. a second difference current detection circuit that selects the polarity of and outputs it as a second difference current; an adder that adds the first and second difference currents to generate a summation output current; and a summation output current. An absolute value circuit characterized by comprising a current-voltage converter that converts current into an output voltage.