JPS6211253A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain connecting structure sufficiently resisting heat and pressure by forming a stress relaxation region onto an insulating film to a wiring layer from the tangential direction of a bump, a plane shape thereof takes a circle, and connecting the wiring layer to the bump through the region. CONSTITUTION:A stress relaxation region 330 extending to a wiring 230 from the tangential direction of a circle is shaped between a circular bump 130 and the wiring 230. An Au thin-layer 35 is laminated onto a Pi layer 33 in the region 330, and a thick Au layer 36 is formed onto the thin-layer 35, thus shaping the bump 130. The circular stress relaxation region displays an effect to breakdown larger than rectangular or tapered one, thus allowing joining having high quality and with high reliability on the simultaneous joining of multi-leads.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a connection structure between an electrode terminal and wiring on a substrate, preferably a connection between an electrode terminal for attaching a large number of lead terminals for external extraction to a semiconductor element, and wiring on a substrate. No. 1: This concerns A construction.

While various methods have been proposed for electrically connecting the electrodes of semiconductor devices and the lead wires to the outside of the container, conventional wires that use thin conductive wires and adhere to the points to be connected to each other have been proposed. Instead of the bonding method, extend the lead wire inside the container, or attach a continuous foil ribbon of metal material to the tape surface made of flexible electrically insulating material, and make a large number of leads from the metal foil. of a semiconductor device with its edges tapered! For example, Japanese Patent Publication No. 47-3206 proposes a method in which a protrusion (bump) is provided on a ti terminal to form an adhesive end sufficient for direct bonding, and the terminal is simultaneously connected to an electrode terminal (bump).

The above connection method involves covering a copper-based lead with tin,
One method is to create a gold/tin eutectic alloy using heat between the bumps whose surface is covered with gold, and the other is to apply heat and pressure between the copper-based lead, which is covered with gold, and the gold bump. There is a thermocompression bonding method that connects the There is a tendency for gold/gold to be used for semiconductor devices that are bonded by thermocompression and that require high reliability as a metal composition, while copper/steel is used for semiconductor devices that require economic efficiency.

Since the method of connecting using thermocompression bonding applies both heat and pressure, a bump with strong mechanical strength is required, and a bump structure with improved mechanical strength is disclosed in JP-A-51-1472.
This is proposed in Publication No. 53. In this method, the panda is configured in a step-like manner, and the relaxation of stress concentration during bonding is considered in terms of the cross-sectional shape, and it has nine effects.

However, in order to sufficiently prevent the destruction of the substrate or the insulating film on the substrate due to stress concentration, it is necessary to consider the stress distribution viewed from the plane of the substrate. It is important because it exists. This must be kept in mind since the stress distribution, that is, the form of stress concentration, is related not only to mechanical factors but also to thermal factors.

In other words, in the past, for the connection between bumps and internal wiring, the wiring width was determined based on the current capacity flowing through the wiring.
The distance between the wiring having a constant width of 11 and the bump to be connected was as short as possible, and the connection portion was also connected to the bump portion while keeping the width of the thin wiring layer. For this reason, when a semiconductor device with a conventional wiring layer and bump connection structure is actually connected to the leads and bumps by thermocompression bonding and a tensile fracture strength test is performed to confirm the connection strength, the failure mode is determined to be due to the bumps. Destruction occurred in the silicon substrate and insulating film at the bottom of the connection area between the internal wiring layer and the internal wiring layer. this is,
This is because stress is concentrated at this connection, and the joint has the possibility of becoming mechanically weak (due to changes over time due to thermal stress, etc.). stomach. An object of the present invention is to provide a new bump-to-wiring connection structure that can sufficiently withstand the heat and pressure applied during thermocompression bonding of leads, while eliminating the above-mentioned drawbacks.

A feature of the present invention is that in a semiconductor device in which a bump (electrode terminal protrusion) portion on an insulating film on a semiconductor substrate is connected to a wiring layer portion having a constant width, the bump portion has a circular planar shape; A planar stress relaxation region that spreads from the wiring layer portion toward the outer diameter of the circular bump is provided on the insulating film, and the wiring layer is connected to the 771 portion via the stress relaxation region. It is a semiconductor device that This stress relaxation region has a first layer having a large planar area, and a second layer provided on the first layer and having a smaller planar surface than the first layer, Second layer KJ: Preferably, a D step portion is formed.

The present invention will be explained below based on the drawings.

1st country, Q3) indicates a semiconductor device according to the conventional technology, 1 indicates a silicon substrate, 2 indicates a silicon oxide film,
An insulating film such as a nitride film, 3 a titanium layer, 4 a platinum layer, 5 a thin gold film for wiring and as an intermediate layer of bumps, and 6 a thick metal film. Further, 100 is a bank portion, and l and 200 are an internal wiring layer portion. A lead (not shown) with a steel base and gold plating on the surface is placed on top of the thick film metal 6 of this bump, and when heat and pressure are applied, the gold on the lead surface and the thick film gold 6 are bonded by thermocompression. It is well joined.

A lead from the bonded semiconductor device was subjected to a tensile test using a tensile strength gauge in a direction perpendicular to the main surface of the semiconductor device to examine the strength and mode of failure.

As a reference for the substrate used in this experiment, a bump with the same shape as in Figure 1 without any wiring was installed in the same semiconductor device, and the rate of destruction of the silicon substrate at the bottom of the bump was investigated under the same bonding conditions. Ta. As a result, in the destruction mode, 2.
It occurred 5 times more. From comparison with reference bumps, it is clear that the occurrence of this defect is influenced by the wiring and its connections. A detailed observation of the fractured silicon substrate at the bottom of the bump in the tensile fracture test revealed that the fracture occurred at the intersection point 7.8 between the outer periphery of the bump and both ends of the wiring.

Here, the heat and pressure applied during bonding are caused by the pressure applied to the bump portion. Due to the fact that concentrated stress and heat can destroy the silicon substrate at the bottom of the connection between the bump and the wiring layer, and in the structure where the wiring is connected to the bank, the heat and pressure applied during thermocompression bonding It is conceivable that heat-induced distortion may be applied to the wiring section. In other words, since the wiring layer is a conductor, it has good thermal conductivity, and the heat applied during bonding is transmitted through the wiring, and there is a large A temperature gradient occurs, and due to this temperature gradient,
Strain (thermal strain) occurs in the substrate underlying the wiring, particularly in the longitudinal direction of the wiring. Furthermore, the present invention was achieved based on the recognition that heat is applied to the wiring through the bump, and therefore is greatest at the wiring near the bump, particularly at the connection between the bump and the wiring. In other words, at the connection between the bump and the wiring, the strain caused by the pressure from the bump, the strain caused by the heat, and the strain caused by the heat from the wiring part are combined to cause a crack in the board, and in a destructive strength test, this crack becomes the nucleus and the board is damaged. It is thought that destruction will occur.

Based on the above theory, the structure of the bump-to-wiring connection portion according to the present invention solves the problem of substrate destruction caused by stress concentration and thermal strain without changing the wiring or bump formation process.

FIG. 2 shows an embodiment of the present invention, in which a stress relaxation region 330 is provided between the circular bump 130 and the wiring section 230, and extends from the tangential direction of the circular shape to the wiring section 230. There is. As is clear from the figure, the stress relaxation region 330 is composed of a region where the first layer 33 and the second layer 35 on the insulating film 32 extend to the wiring portion. The structure of this embodiment is expected to be more effective against fracture than a rectangular parallelepiped or tapered planar stress relaxation region. In this embodiment, a bump 130 having a two-step shape is composed of a first layer 33 made of titanium or platinum, a 20th layer 35 made of thin metal thereon, and a third layer 36 made of thick gold thereon. be done. The stress relief region 330 is formed from this first layer and the second layer 1-,
As is clear from the figure, it has a one-stage configuration. The wiring section 230 has a stepless shape due to the first layer and the second layer having the same planar shape.

The present invention makes it possible to realize a connection structure between electrode terminals and wiring that can withstand high temperatures and pressures without changing the conventional wiring manufacturing process, and allows for a wider selection of bonding metals for leads and bumps, resulting in high quality, Reliable bonding is now possible. In addition, it becomes possible to simultaneously bond high-quality, inexpensive, large-scale integrated semiconductor devices with a large number of leads, which is of extremely great industrial significance. Further, in the embodiment, the bank portion has a two-step shape, but the present invention is of course not limited to this, and may have one step, no steps, or multiple steps of three or more steps. Further, the stress relaxation region is not limited to a single stage shape, but may be stepless or multistaged with two or more stages.

Furthermore, the electrically conductive layers in the bank part, stress relaxation area part, and wiring layer part are not limited to the examples, and in some cases, the corresponding layers in each part may be formed successively using different materials. You may.

[Brief explanation of drawings]

FIG. 1(B) is a plan view and a side view showing a semiconductor device according to the prior art. FIG. 2 is a plan view showing an embodiment of the present invention. In the figure, 1 is the silicon substrate, 2% 32 is the insulating film, 3 is the titanium layer, 4 is the white metal, 7.8 is the intersection of the bump outer periphery and both ends of the wiring, 33 is the bottom layer, and 35 is the bump. 36 is the uppermost layer of the bump part, 100, 130 is) < 71 part, 200, 230
330 is a wiring layer portion, and 330 is a stress relaxation region.

Claims (2)

[Claims] (1) In a semiconductor device in which a bump portion on an insulating film on a semiconductor substrate is connected to a wiring layer portion of a constant width, the bump portion has a circular planar shape, and the wiring layer portion is connected from the tangential direction of the bump. A semiconductor device characterized in that a stress relaxation region is provided on the insulating film toward the bump portion, and the wiring layer is connected to the bump portion via the stress relaxation region. (2) The stress relaxation region has a first layer having a large planar area, and a second layer provided on the first layer and having a smaller planar surface than the first layer, and Claim 1, characterized in that the layer and the second layer form a stepped portion.
1) The semiconductor device described in item 1).