JPS6211159Y2 - - Google Patents

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Publication number
JPS6211159Y2
JPS6211159Y2 JP13273579U JP13273579U JPS6211159Y2 JP S6211159 Y2 JPS6211159 Y2 JP S6211159Y2 JP 13273579 U JP13273579 U JP 13273579U JP 13273579 U JP13273579 U JP 13273579U JP S6211159 Y2 JPS6211159 Y2 JP S6211159Y2
Authority
JP
Japan
Prior art keywords
phase
voltage
circuit
transistor
load current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13273579U
Other languages
Japanese (ja)
Other versions
JPS5651437U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP13273579U priority Critical patent/JPS6211159Y2/ja
Publication of JPS5651437U publication Critical patent/JPS5651437U/ja
Application granted granted Critical
Publication of JPS6211159Y2 publication Critical patent/JPS6211159Y2/ja
Expired legal-status Critical Current

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Description

【考案の詳細な説明】 本考案は三相モータなどの欠相事故を検出し、
モータの保護を行う欠相検出回路に関するもので
ある。
[Detailed description of the invention] This invention detects open-phase accidents in three-phase motors, etc.
The present invention relates to an open phase detection circuit that protects a motor.

従来のこの種の回路は、負荷電流を整流して、
そのリツプル変化を検出するリツプル方式や、正
相分と逆相分との比較による方式など種々あるが
波形歪の影響を受けやすいとか、反相と欠相が分
離検出できないなどの不具合があつた。
Conventional circuits of this type rectify the load current and
There are various methods such as the ripple method that detects the ripple change and the method that compares the positive and negative phase components, but these methods have problems such as being susceptible to waveform distortion and not being able to detect the negative phase and the missing phase separately. .

本考案は上記欠点を改良しようとするものであ
り、以下に図面に基づいて説明する。
The present invention aims to improve the above-mentioned drawbacks, and will be explained below based on the drawings.

第1図は本考案の一実施例であり、図において
R1〜R13は抵抗、CT1,CT2は変流器、TR1〜TR4
はトランジスタ、IC1〜IC3はアンド素子、IC4
オア素子、IC5は比較増幅器、D1〜D6はダイオー
ド、C1〜C3はコンデンサ、RAは継電器、Eは直
流電源である。
Figure 1 shows an embodiment of the present invention, and in the figure
R 1 to R 13 are resistors, CT 1 and CT 2 are current transformers, TR 1 to TR 4
are transistors, IC 1 to IC 3 are AND elements, IC 4 is an OR element, IC 5 is a comparison amplifier, D 1 to D 6 are diodes, C 1 to C 3 are capacitors, RA is a relay, and E is a DC power supply. .

負荷電流を検出する変流器CT1,CT2の2次端
子は、抵抗R1,R2に各々接続され、さらにV結
線されることにより、負荷電流を3相の電圧に変
換する。
The secondary terminals of the current transformers CT 1 and CT 2 that detect the load current are connected to resistors R 1 and R 2 , respectively, and further V-connected to convert the load current into three-phase voltage.

前記3相電圧の第1相は、抵抗R3を介してト
ランジスタTR1のベースに印加され、同様に第2
相は抵抗R4を介してトランジスタTR2のベース
に、第3相は抵抗R5を介してトランジスタTR3
ベースに各々印加される。
The first phase of said three-phase voltage is applied to the base of transistor TR 1 via resistor R 3 and likewise the second phase.
The third phase is applied to the base of the transistor TR 2 via the resistor R 4 and the third phase is applied to the base of the transistor TR 3 via the resistor R 5 .

ダイオードD1〜D3は、前記トランジスタTR1
〜TR3のベース・エミツタ間の逆電圧保護用ダイ
オードである。
The diodes D 1 to D 3 are connected to the transistor TR 1
~ This is a reverse voltage protection diode between the base and emitter of TR 3 .

前記トランジスタTR1のコレクタは抵抗R6を介
して直流電源Eに接続されているため、前記3相
電圧の第1相が正になるとトランジスタTR1
ON状態となり、コレクタ電位は低電位となる。
逆に前記3相電圧の第1相が負になると前記トラ
ンジスタTR1はOFF状態になり、コレクタ電位
は高電位となる。
Since the collector of the transistor TR1 is connected to the DC power supply E via the resistor R6 , when the first phase of the three-phase voltage becomes positive, the transistor TR1
It becomes ON state and the collector potential becomes low potential.
Conversely, when the first phase of the three-phase voltage becomes negative, the transistor TR1 is turned off and the collector potential becomes high.

即ち、トランジスタTR1は前記3相電圧の第1
相電圧が正になるか負になるかによつてON.OFF
をくり返し、前記第1相電圧に同期をとつたパル
スを発生する。
That is, the transistor TR1 is connected to the first voltage of the three phase voltages.
ON/OFF depending on whether the phase voltage becomes positive or negative
This is repeated to generate a pulse synchronized with the first phase voltage.

同様に前記トランジスタTR2は、前記3相電圧
の第2相電圧に同期をとつたパルスを発生し、前
記トランジスタTR3は前記3相電圧の第3相電圧
に同期をとつたパルスを発生する。(第2図V1
V2,V3参照) 前記トランジスタTR1のコレクタはアンド素子
IC1とIC3のゲートに接続され、同様に前記トラン
ジスタTR2のコレクタはアンド素子IC1とIC2のゲ
ートに、前記トランジスタTR3のコレクタはアン
ド素子IC2とIC3のゲートに各々接続されている。
即ち、アンド素子IC1は、前記3相電圧の第1相
電圧と第2相電圧が両方とも負のときだけ高電位
信号を出力する。同様にアンド素子IC2は第2相
電圧と第3相電圧が両方とも負のときだけ高電位
信号を出力し、アンド素子IC3は第3相電圧と第
1相電圧が両方とも負のときだけ高電位信号を出
力する。前記アンド素子IC1〜IC3の各出力は、オ
ア素子IC4のゲートに各々入力され、各相の各々
の重なり角が高電位信号として出力される(第2
図V4)。又、前記オア素子IC4の出力は抵抗R9
コンデンサC1より構成される積分回路に接続さ
れ、前記各相の重なり角信号は三角波信号に変換
される(第2図V5)。
Similarly, the transistor TR 2 generates a pulse synchronized with the second phase voltage of the three-phase voltage, and the transistor TR 3 generates a pulse synchronized with the third phase voltage of the three-phase voltage. . (Fig. 2 V 1 ,
(See V 2 , V 3 ) The collector of the transistor TR 1 is an AND element.
Similarly, the collector of the transistor TR 2 is connected to the gates of AND elements IC 1 and IC 2 , and the collector of the transistor TR 3 is connected to the gates of AND elements IC 2 and IC 3 . has been done.
That is, the AND element IC 1 outputs a high potential signal only when the first phase voltage and the second phase voltage of the three-phase voltages are both negative. Similarly, AND element IC 2 outputs a high potential signal only when the second phase voltage and third phase voltage are both negative, and AND element IC 3 outputs a high potential signal only when the third phase voltage and first phase voltage are both negative. outputs a high potential signal. The respective outputs of the AND elements IC 1 to IC 3 are input to the gate of the OR element IC 4 , and each overlap angle of each phase is output as a high potential signal (second
Figure V4 ). Further, the output of the OR element IC 4 is connected to an integrating circuit composed of a resistor R 9 and a capacitor C 1 , and the overlapping angle signals of each phase are converted into triangular wave signals (V 5 in FIG. 2).

前期積分回路の中点は、コンデンサC2、ダイ
オードD5、抵抗R10より構成される微分回路に接
続され、前記三角波信号のリツプル電圧を検出す
る。前記抵抗R10に並列接続されたコンデンサC3
は平滑コンデンサであり、前記ダイオードD5
前記コンデンサC3の放電防止用ダイオードであ
る。またダイオードD4は、前記コンデンサC2
放電用ダイオードである。
The midpoint of the first integrating circuit is connected to a differentiating circuit composed of a capacitor C 2 , a diode D 5 , and a resistor R 10 to detect the ripple voltage of the triangular wave signal. Capacitor C 3 connected in parallel with said resistor R 10
is a smoothing capacitor, and the diode D5 is a diode for preventing discharge of the capacitor C3 . Further, the diode D4 is a diode for discharging the capacitor C2 .

前記抵抗R10の電圧は比較増幅器IC5に入力さ
れ、抵抗R11とR12により構成される分圧回路によ
つて決まる電圧(以下基準電圧という)と比較さ
れる。前記比較増幅器IC5の出力は抵抗R13を介し
てトランジスタTR4のベースに接続されている。
前記トランジスタTR4のコレクタは、継電器RA
を介して直流電源Eに接続されている。前記継電
器RAに並列接続されているダイオードD6はトラ
ンジスタTR4のサージ保護用ダイオードである。
The voltage of the resistor R10 is input to the comparison amplifier IC5 , and is compared with a voltage (hereinafter referred to as reference voltage) determined by a voltage dividing circuit constituted by resistors R11 and R12 . The output of the comparison amplifier IC 5 is connected to the base of the transistor TR 4 via a resistor R 13 .
The collector of the transistor TR 4 is connected to the relay RA
It is connected to the DC power supply E via. A diode D6 connected in parallel to the relay RA is a surge protection diode for the transistor TR4 .

負荷電流が平衡3相電流の場合、各相の重なり
角は60゜であり、第2図のV4の如く60゜ずつの
ON・OFF信号となる。前記60゜ずつのON・
OFF信号は前記積分回路で三角波に変換され、
リツプル電圧のみが前記微分回路で検出される。
検出されたリツプル電圧は前記比較増幅器IC5
比較されるが、前記基準電圧の方が高く設定され
ているので出力は低電位のままである。即ち、前
記トランジスタTR4はOFF状態であり、前記継
電器RAも無励磁状態である。
When the load current is a balanced three-phase current, the overlapping angle of each phase is 60°, and the overlap angle of each phase is 60° as shown in V 4 in Figure 2.
It becomes an ON/OFF signal. 60° each ON・
The OFF signal is converted into a triangular wave by the integration circuit,
Only the ripple voltage is detected by the differentiating circuit.
The detected ripple voltage is compared in the comparison amplifier IC 5 , but since the reference voltage is set higher, the output remains at a low potential. That is, the transistor TR4 is in an OFF state, and the relay RA is also in a non-energized state.

次に例えばS相が欠相した場合、前記3相電圧
の第1相と第3相は同位相となり、各相の重なり
角は180゜となる。第3図のV4の如く180゜ずつ
のON・OFF信号となり、同様に三角波に変換さ
れてリツプル電圧が検出されるが、平衡3相時の
リツプル電圧に比べ欠相時のリツプル電圧は大き
くなつている。従つて、前記基準電圧は欠相時の
リツプル電圧より低めに設定されているので、前
記比較増幅器IC5の出力は、高電位となつて検出
信号を出力する。
Next, for example, if the S phase is open, the first and third phases of the three-phase voltage will be in phase, and the overlapping angle of each phase will be 180 degrees. As shown in V 4 in Figure 3, it becomes an ON/OFF signal in 180° increments, and is similarly converted into a triangular wave to detect ripple voltage, but the ripple voltage during an open phase is larger than the ripple voltage during balanced three-phase operation. It's summery. Therefore, since the reference voltage is set lower than the ripple voltage at the time of phase loss, the output of the comparison amplifier IC 5 becomes a high potential and outputs a detection signal.

即ち、前記トランジスタTR4はON状態となり
前記継電器RAも励磁されて欠相検出信号が出力
される。また前記基準電圧を適当に設定すること
によつて、第4図の如く、不平衡も検出できるこ
とは言うまでもない。
That is, the transistor TR4 is turned on, the relay RA is also excited, and an open phase detection signal is output. It goes without saying that by appropriately setting the reference voltage, it is also possible to detect unbalance as shown in FIG.

以上説明したように、本考案は各相電流の重な
り角を検出して、その重なり角の変化をリツプル
電圧に変換して欠相あるいは不平衡の検出を行な
つているため、負荷電流が歪んだ波形であつても
影響をうけないのは言うまでもない。
As explained above, the present invention detects the overlapping angle of each phase current and converts the change in the overlapping angle into ripple voltage to detect open phase or unbalance, so the load current is not distorted. Needless to say, even if the waveform is different, it will not be affected.

なお本実施例は、アンド素子とオア素子による
説明を行なつたが、ナンド素子とかノア素子を使
用しても同様の効果が得られるのはいうまでもな
い。
Although this embodiment has been described using an AND element and an OR element, it goes without saying that similar effects can be obtained by using a NAND element or a NOR element.

また、上記実施例においては負荷電流を検出す
るのに変流器を2個使用する場合について図示説
明したが、3個使用しても同様の効果が得られる
のは勿論である。
Further, in the above embodiment, the case where two current transformers are used to detect the load current has been illustrated and described, but it goes without saying that the same effect can be obtained even if three current transformers are used.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は平衡時の動作パターン図、第3図は欠相時の
動作パターン図、第4図は不平衡時の動作パター
ン図である。 なお、図中R1〜R13は抵抗、CT1,CT2は変流
器、TR1〜TR4はトランジスタ、IC1〜IC3はアン
ド素子、IC4はオア素子、IC5は比較増幅器、D1
〜D6はダイオード、C1〜C3はコンデンサ、RAは
継電器、Eは直流電源である。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure shows an operation pattern during balanced operation, FIG. 3 shows an operation pattern during open phase, and FIG. 4 shows an operation pattern during unbalanced operation. In the figure, R 1 to R 13 are resistors, CT 1 and CT 2 are current transformers, TR 1 to TR 4 are transistors, IC 1 to IC 3 are AND elements, IC 4 is an OR element, and IC 5 is a comparison amplifier. , D 1
~ D6 is a diode, C1 ~ C3 are capacitors, RA is a relay, and E is a DC power supply.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 負荷電流検出器によつて検出された三相負荷電
流の各相夫々について正であるか負であるかを判
別してこの三相負荷電流の各相夫々の正負に対応
したパルス信号を夫々出力するパルス発生回路
と、前記パルス発生回路の各出力を入力として各
相の重なり角に応じた一つのパルス信号を出力す
る重なり角検出回路と、この検出回路の出力を積
分して三角波信号とするCR積分回路とを備え、
前記CR積分回路のリツプル電圧を検出すること
により三相回路の欠相あるいは不平衡を検出する
ことを特徴とする欠相検出回路。
Determines whether each phase of the three-phase load current detected by the load current detector is positive or negative, and outputs a pulse signal corresponding to the positive or negative of each phase of the three-phase load current. an overlap angle detection circuit that receives each output of the pulse generation circuit as input and outputs one pulse signal according to the overlap angle of each phase, and integrates the output of this detection circuit to generate a triangular wave signal. Equipped with a CR integration circuit,
An open phase detection circuit characterized in that an open phase or unbalanced phase in a three-phase circuit is detected by detecting the ripple voltage of the CR integrating circuit.
JP13273579U 1979-09-26 1979-09-26 Expired JPS6211159Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13273579U JPS6211159Y2 (en) 1979-09-26 1979-09-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13273579U JPS6211159Y2 (en) 1979-09-26 1979-09-26

Publications (2)

Publication Number Publication Date
JPS5651437U JPS5651437U (en) 1981-05-07
JPS6211159Y2 true JPS6211159Y2 (en) 1987-03-16

Family

ID=29364342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13273579U Expired JPS6211159Y2 (en) 1979-09-26 1979-09-26

Country Status (1)

Country Link
JP (1) JPS6211159Y2 (en)

Also Published As

Publication number Publication date
JPS5651437U (en) 1981-05-07

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