JPS62111534A - Agc circuit - Google Patents
Agc circuitInfo
- Publication number
- JPS62111534A JPS62111534A JP60251033A JP25103385A JPS62111534A JP S62111534 A JPS62111534 A JP S62111534A JP 60251033 A JP60251033 A JP 60251033A JP 25103385 A JP25103385 A JP 25103385A JP S62111534 A JPS62111534 A JP S62111534A
- Authority
- JP
- Japan
- Prior art keywords
- apd
- circuit
- mean
- agc circuit
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Optical Communication System (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、光通信において、安定した信号を受信再生で
きる光受信機のＡＧＣ回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an AGC circuit for an optical receiver that can receive and reproduce stable signals in optical communications.
（従来の技術）
第２図は、従来のＡＧＣ回路を示している。同図におい
て１１はＡＰＤ、１２はＡＰＤＩＩの信号電流を電圧変
換・増幅するプリアンプ、１３は増幅器、■４は直流再
生のためのクランプ回路、 １５はピーク値検出回路、
１６はピーク値検出回路１５の出力と基準電圧を比較増
幅する増幅器、１７はＡＰＤＩＩのバイアス用ＤＣ１０
Ｃコンバータである。(Prior Art) FIG. 2 shows a conventional AGC circuit. In the figure, 11 is an APD, 12 is a preamplifier that converts and amplifies the signal current of APDII, 13 is an amplifier, 4 is a clamp circuit for DC regeneration, 15 is a peak value detection circuit,
16 is an amplifier that compares and amplifies the output of the peak value detection circuit 15 and the reference voltage, and 17 is a DC 10 for biasing APDII.
It is a C converter.
ＡＰＤＩＩの信号電流をプリアンプ１２および増幅器１
３で電圧変換増幅し、クランプ回路１４で直流再生し、
ピーク値検出回路１５で信号のピーク値または振幅が検
出され、この出力と基準電圧が増幅器１６で比較増幅さ
れＤＣ／ＤＣコンバータ１７を制御することにより、光
信号が変動しても出力信号１８が常に安定して一定の振
幅値を保つことが可能である６（発明が解決しようとす
る問題点）
上記構成においては、直流再生のためのクランプ、信号
レベル検出のためのピーク値検出が必要であり、信号帯
域が高くなるにしたがい、回路の実現が困難になる欠点
があった６
本発明の目的は、従来の欠点を解消し、直流レベルで簡
単な回路構成により実現できるＡＧＣ回路を提供するこ
とである。The APD II signal current is transferred to the preamplifier 12 and amplifier 1.
3 performs voltage conversion and amplification, clamp circuit 14 performs DC regeneration,
The peak value or amplitude of the signal is detected by the peak value detection circuit 15, and this output and the reference voltage are compared and amplified by the amplifier 16. By controlling the DC/DC converter 17, the output signal 18 can be maintained even if the optical signal fluctuates. It is possible to always maintain a constant amplitude value stably.6 (Problem to be solved by the invention) In the above configuration, a clamp for DC reproduction and a peak value detection for signal level detection are required. However, as the signal band becomes higher, it becomes difficult to implement the circuit.6 The object of the present invention is to eliminate the conventional drawbacks and provide an AGC circuit that can be realized with a simple circuit configuration at the DC level. That's true.
（問題点を解決するための手段）
本発明のＡＧＣ回路ば、ＡＰＤとその出力平均直流電流
を検出する電流検出回路とこの出力と基準電圧を比較増
幅し、ＡＰＤのバイアス電圧を発生する増幅回路、ＤＣ
／ＤＣコンバータよりなるものである。(Means for Solving the Problems) The AGC circuit of the present invention includes a current detection circuit that detects an APD and its output average DC current, and an amplifier circuit that compares and amplifies this output with a reference voltage and generates a bias voltage for the APD. , D.C.
/DC converter.
（作 用）
平均直流検出器によって直流ＡＰＤを制御するようにし
てあり、またＡＧＣ回路系がすべて直流系で構成される
ため回路が簡単となり、動作も安定する。(Function) The DC APD is controlled by the average DC detector, and since the AGC circuit system is entirely composed of DC systems, the circuit is simple and the operation is stable.
（実施例） 本発明の一実施例を第１図に基づいて説明する。(Example) An embodiment of the present invention will be described based on FIG.
第１図は本発明のＡＧＣ回路のブロック図である。FIG. 1 is a block diagram of the AGC circuit of the present invention.
同図において、１はＡＰＤ、２はＡＰＤ １の信号電流
を電圧変換増幅するプリアンプ、３はその出力端子。In the figure, 1 is an APD, 2 is a preamplifier that converts and amplifies the signal current of APD 1, and 3 is its output terminal.
４はＡＰＤ １の平均直流電流検出器、５は平均直流電
流検出器４の出力と基準電圧を比較増幅する増幅器、６
はＡＰＤバイアス用のＤＣ／ＤＣコンバータである。Ａ
ＰＤ １の信号電流の平均値を平均直流電流検出器４で
検出し、この電圧と基準電圧を比較増幅し、ＤＣ／ＤＣ
コンバータ６を制御することにより、ＡＰＣＩの増倍数
を制御し、光入力信号の変動に対し常にＡＰＤ １の平
均直流が一定となるように負帰還が働きＡＧＣ制御が行
なわれるものである。4 is the average DC current detector of APD 1, 5 is an amplifier that compares and amplifies the output of the average DC current detector 4 and the reference voltage, 6
is a DC/DC converter for APD bias. A
The average value of the signal current of PD 1 is detected by the average DC current detector 4, this voltage is compared and amplified with the reference voltage, and the DC/DC
By controlling the converter 6, the APCI multiplication number is controlled, and negative feedback is activated so that the average direct current of the APD 1 is always constant despite fluctuations in the optical input signal, and AGC control is performed.
（発明の効果）
本発明によれば、ＡＧＣ回路系がすへて直流系で構成さ
れるため回路が簡単となり、この簡略化により動作が安
定する効果がある。(Effects of the Invention) According to the present invention, since the AGC circuit system is entirely composed of a DC system, the circuit is simplified, and this simplification has the effect of stabilizing the operation.
第１図は本発明の一実施例によるＡＧＣ回路のブロック
図、第２図は従来のＡＧＣ回路のブロック図である。
１ ・・・ＡＰＤ、 ２ ・・・プリアンプ、 ３ ・
・・出力端子、 ４ ・・・平均直流電流検出器、５
・・・増幅器、 ６ ・・・ＤＣ／ＤＣコンバータ。FIG. 1 is a block diagram of an AGC circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional AGC circuit. 1...APD, 2...Preamplifier, 3.
...Output terminal, 4 ...Average DC current detector, 5
...Amplifier, 6...DC/DC converter.
Claims (1)
、該ＡＰＤの出力平均直流を検出する電流検出回路と、
該電流検出回路の出力と基準電圧を比較増幅し、前記Ａ
ＰＤのバイアス電圧を発生する増幅回路と、ＡＰＤバイ
アス用ＤＣ／ＤＣコンバータよりなることを特徴とする
ＡＧＣ（自動利得制御）回路。an avalanche photodiode (hereinafter referred to as APD); a current detection circuit that detects the average DC output of the APD;
The output of the current detection circuit and the reference voltage are compared and amplified, and the
An AGC (automatic gain control) circuit comprising an amplifier circuit that generates a PD bias voltage and an APD bias DC/DC converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60251033A JPS62111534A (en) | 1985-11-09 | 1985-11-09 | Agc circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60251033A JPS62111534A (en) | 1985-11-09 | 1985-11-09 | Agc circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62111534A true JPS62111534A (en) | 1987-05-22 |
Family
ID=17216613
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60251033A Pending JPS62111534A (en) | 1985-11-09 | 1985-11-09 | Agc circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62111534A (en) |
-
1985
- 1985-11-09 JP JP60251033A patent/JPS62111534A/en active Pending
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