JPS6211151A - Apparatus for inspecting surface flaw - Google Patents

Abstract

PURPOSE:To enhance the detection accuracy of the min. flaw up to a micron order, by directly detecting scattering light generated at the flaw part on the surface of an article to be detected and passing the same through LPF to separate and extract a flaw of a distribution state at an early stage. CONSTITUTION:A semiconductive wafer 6 as an article to be detected is placed on a feed stage 81 and fed to a Y-direction at a constant speed. A laser beam scanning means 28 is constituted so that the surface 6s of the wafer 6 is scanned in a main scanning direction with laser beam 82. A cylindrical lens 9 receives only scattering beam irregularly reflected from the surface 6s of the wafer 6 and allows the same to converge to the incident window of an optical fiber bundle 97 while the guided scattering beam is emitted to a photomultifier tube 2 and the flaw signal relating to low-frequency led out from the photomultiplier tube 2 is detected at an early stage through LPF.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a surface defect inspection device, particularly for detecting minute defects (pinholes, etc.) on the surface of magnetic disks, optical disks, semiconductor wafers, dry plates for hard masks, etc. This invention relates to a surface defect inspection device that automatically inspects dust, scratches, etc.) with high precision.

i Convex skin! When detecting surface defects of a specimen such as a sea urchin by scanning a light beam such as a laser, the S/N ratio is lower than the method of detecting defects on the surface by detecting a decrease in specularly reflected light. Because of the height, it is advantageous to directly detect scattered light generated by defects such as scratches and dust on the surface. but,
The absolute amount of scattered light is extremely small compared to specularly reflected light. Various problems are encountered when detecting this minute scattered light and extracting defect signals with high accuracy.

Furthermore, it becomes even more difficult under the condition that high costs are not caused.

On the other hand, in recent years, as the integration of semiconductor devices has progressed further and line widths have become finer to 2μ, 1μ, and even submicrons, defect sizes that were previously allowed on the micron order have become smaller in terms of yield. Submicron precision is increasingly required. Considering this requirement and the above-mentioned scattered light direct detection method, this type of surface defect inspection apparatus requires various unique technical innovations.

Based on the above background, the general purpose of the present invention is to directly detect the scattered light generated at the defective part on the surface of the test object, perform signal processing, and achieve a minimum defect detection accuracy of submicron order. An object of the present invention is to provide a new device capable of inspecting surface defects at a low cost.

The main purpose of the present invention is to eliminate ff1z that exists together with noise.
k&shin Jk#-chishinbunsha's entry winter fin liao upper Z sleeve lJ, p By inventing the signal processing system and making it possible to obtain defective signals with good stability and high precision. be.

Another object of the present invention is to enable efficient signal processing depending on the nature of surface defects.

Furthermore, another purpose is to effectively communicate the obtained defect data as visualization information so that the defect occurrence situation can be accurately grasped.

i Skin convex serum! To summarize the present invention, there is provided a photoelectric signal output means for outputting an electric signal according to the intensity of light diffusely reflected by a defective part on the surface of a test object scanned by a laser beam; a first signal processing means that performs signal averaging processing on the Dinotal signal sequentially in the main scanning direction and then in the sub-scanning direction to suppress noise components; tJII2 signal processing means for creating shading correction data based on the data and performing shading correction in real time on the output of the first signal processing means, or a defect on the surface of the object scanned by the laser beam. a photoelectric signal output means for outputting an electric signal according to the intensity of the light diffusely reflected by the photoelectric signal output means; and a second photoelectric signal output means for performing 7-nalog-to-day nottal conversion on the output signal of the photoelectric signal output means and performing shading correction in real time.
and the output of this second signal processing means,
and a first signal processing means for suppressing noise components by sequentially averaging signals in the main scanning direction and then in the sub-scanning direction, and removing high frequency components from the output of each of the latter signal processing means. a circuit for providing a base signal for signal comparison; a plurality of adder circuits for adding a plurality of preset different level signals to the base signal; and outputs of the respective adder circuits and signal processing means for each of the latter. The basic feature is that the third signal processing means is provided with a third signal processing means having a comparison circuit that compares the output of do.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the basic features of the present invention described above, including other features, will be specifically explained with reference to embodiments shown in the accompanying drawings.

The tISi diagram is a perspective view showing an example of an optical system of a semiconductor wafer surface defect inspection apparatus as an example.

As shown in the figure, a semiconductor wafer (6) as a test object is
The wafer is placed on a transport stage (81) that is driven in a constant Y direction, and is transported in the Y direction at a constant speed, for example, 5 mm/s. The surface (6s) is scanned in the main scanning direction.Synchronized with the scanning of this laser beam (7),
Conveyance of the wafer (6) in the sub-scanning direction (Y direction) is controlled.

The laser beam scanning means (82) is configured, for example, on two upper and lower surface plates (83) and (84), and a He Ne laser (85) with a wave i of 633 nm is used as a light source, for example. Is the emitted beam of the He-Ne laser (85) reflected? (86a) and (86b), the beam is deflected by 18 degrees and enters the beam expander (87). The laser beam whose beam diameter has been expanded by the beam expander (87) is deflected downward by a reflecting mirror (88a), passes through a hole (83h) in a surface plate (83), and is then horizontally deflected by a reflecting mirror (88b). Deflected and vibrating mirror (89
). The vibrating mirror (89) is, for example, 200
It vibrates at Hz and swings the laser beam left and right in a horizontal plane.

The laser beam swung left and right by the vibrating mirror (89) is
The reflecting mirror (90) converges the beam to a predetermined beam diameter on the semiconductor wafer (6) and the grating (94) to be described later.
91). From the vibrating mirror (89) to the imaging lens (
The laser beam incident on the reflecting mirror (91) via the reflecting mirror (90) is deflected downward at right angles by the reflecting mirror (91), passes through the long hole (84h) of the surface plate (84), and is directed onto the wafer surface (6s). For example, a predetermined beam diameter of 50 μl
Scan the surface (6s) with φ. The beam spot of the 50μ ship φ draws a scanning line (8) as its locus (hereinafter, the scanning line may be referred to as a scanning line or simply a line, and in correspondence with the scanning line by the laser beam, one scanning line) electrical signals).

Between the imaging lens (90) and the reflecting mirror (91),
A half mirror (92) is provided, and a part of the laser beam is sent to a grating (94) via a reflecting mirror (93).
is leading to A photosensor 7 array (95) is provided on the back side of the grating (94), and the output of this photosensor array (95) is used as a reference clock for a signal processing system to be described later.

(96) is a cylindrical lens, and the wafer surface (6
s) parallel to the laser beam scanning direction (main scanning direction),
Entrance window (97W) for wafer (6) and optical fiber bundle (97)
) is fixed at a predetermined location between the This cylindrical lens (96) has a dimension longer than the effective scanning width (determined by the amplitude of the oscillating mirror (89)) on the wafer surface (6s) on the wafer surface (6s) over which the laser beam (7)
The light specularly reflected by 6s) is not received, but only the scattered light reflected by 6L is received, and the light received from one scanning line is condensed into a linear shape. Scattered light that is diffusely reflected by defects (scratches, dust, etc.) on the wafer surface (6s) is focused by a cylindrical lens (96), and the light is 7 ft/? It is converged at the entrance window (97W) of the bundle (97).

The optical fiber bundle (97) as a light guiding means is connected to the entrance window (9
On the opposite side of the head-on type photomultiplier tube (2)
The scattered light is focused to fit the shape of the head of the head, and the guided scattered light is emitted from the head window (2W) to the photomultiplier tube (2). As is well known, the photomultiplier tube (2) has the highest detection sensitivity and excellent time response as a photoelectric conversion means. It is ideal for detecting weak scattered light and high-speed signal processing. The optical fiber east (97) as the light guiding means is provided so that this photomultiplier tube (2) can be used, and if a slight deterioration of the S/N ratio is tolerated, the optical fiber east (97) can be used. The fiber bundle (97) may be omitted and a photoelectric conversion element, such as a one-dimensional COD photo7 ray sensor, may be provided directly at the condensing and imaging position of the cylindrical lens (96).

In addition, the absolute amount of diffused ML light input to the photoelectric conversion means can be increased (
For this purpose, a concave mirror with a spherical cross section may be disposed on the opposite side of the cylindrical lens (98) across the scanning line (8), or another pair of condensing optics and systems may be disposed. It's okay. Furthermore, if multiple cylindrical lenses (96) are used in combination, (effective width of lens system)/(
The larger the ratio of the focal length (focal length), the larger the angle of view of the cylindrical lens, which increases the absolute amount of scattered light received.

Next, for the purpose of relating it to the signal processing system described below,
The outline of the inspection will be illustrated using a 6-inch diameter wafer as an example.

As shown in FIG. 2, the surface (6s) of a wafer (6) with a diameter of 6 inches is, for example, 150 mm x 150 mur (7).
The inspection is performed while the laser beam scans the laser beam scanning area (6-i). The width of the scanning laser beam (7 sp) is 50 μmφ, but as shown in FIG. 3, slow speed control is performed so that each scanning line overlaps by 25 μm in the sub-scanning direction.

The scattered light of the laser beam on the wafer surface (6s) is
The photomultiplier tube (2) (see Figure 1) converts the signal into an analog signal, which includes pulsed signals corresponding to discrete defects and pulsed signals as shown in Figure 6(a). 1
There are also distributed signals corresponding to distributed defects.

Therefore, in a preferred embodiment of the present invention, these two types of signals are separated into two systems, and a defective signal is extracted from each system. That is, for the above-mentioned pulsed signal, the minimum detection unit is 50 μm×50 μl, and the presence/absence of a defect and the level of its size in this detection unit are determined.

On the other hand, for the above-mentioned distributed signal, the presence/absence of a defect is determined using the minimum detection unit of 50 μm x 500 μm.

For these two types of defect detection modes, Fig. 2 shows (6a)
Defect data is obtained using a micro-section area of 0, 5 mmX O, 5n+m as a common unit. That is,
For pulsed signals, as shown in Fig. 4 (al) to (a3), the unit section area (6a) is divided into 10XI O (small detection unit (6al+)), and in this divided area. , as shown in corresponding FIGS. 4(aal) to (aa3), three different levels are set in advance and it is detected which level the defect signal is at (see FIG. 4(a)).
In each of (1) to (a3), the presence of a defective signal exceeding the corresponding level is indicated by diagonally hatching the pixel).

The defect data in the unit section area (6a) is represented by the largest defect data. In the illustrated example, the defect data is level 3. Therefore, the defect data related to this pulsed signal includes level O (no defect), level 1. Level 2. Four types of level 3 are specified.

On the other hand, for distributed signals, as shown in FIG. 4(b), the minimum detection unit ( 6al)
), it is detected how many defects (the presence of defects is similarly indicated by diagonal lines) in these 10 ranges. The detection is shown in the same figure (b
As shown in b), it is determined whether the distributed defect signal exceeds level C1.

The detected result (the number of pieces is “8” in the example shown with diagonal lines in FIG. 4(b)) is determined by the preset number data (for example, “6”).
) as defect data related to low frequencies in the unit section area (6al). Therefore, this data is defined as a binary value of defective/defectless.

As defined above, the defect data is 150am
300X in the scanning area (61) of 150wt&
Obtained as 300 two types of data groups.

Therefore, the micro section area (6a) on the wafer surface (6s)
and, for example, the pixel (or dot) position (X, Y) of a CRT monitor (75) as shown in FIG. 5, and replace the above data group with 300×300 visualization information.

A color monitor is used as the CRT monitor (75), and colors are displayed according to the type of defect data.

In the present device according to a preferred embodiment, after separating the analog signal obtained from the photomultiplier tube (2) into two systems, both are converted into digital signals, so that signal processing progresses stably. As a result, highly accurate defect data can be obtained and high inspection accuracy can be achieved, and at the same time, since the data is displayed in color, the efficiency of the inspection process can also be improved.

FIG. 7 shows an overall block diagram of the signal processing system.

Circuit (1) uses a photomultiplier tube (P) as a photoelectric sensor.
MT) (2) included, scattered i! A photoelectric signal output circuit that outputs an electric signal (So) according to the intensity of iL light,
2) An amplifier circuit (
3), a protection circuit (4) that detects changes in the output of the amplifier circuit (3) and protects the PMT (2) from excessive input;
It is configured to include a high voltage power supply circuit (5) that supplies a high voltage to T (2), and outputs an analog voltage signal (So) from an amplifier circuit (3).

From this circuit (1), via the Δ/D conversion circuit (11),
Circuit (10), Circuit (20), Circuit (aO), Circuit (4
0) and the signal path leading to the circuit (60) detects high-frequency pulse-like signals corresponding to discrete defects (scratches, dents, adhesion of dust, etc.) on the wafer surface, and converts this into data. . On the other hand, the signal path from circuit (1) to circuit (50) is caused by distributed defects (fingerprints, grease, etc.) on the wafer surface.

Detects low-frequency defect signals that correspond to cloudiness or smear caused by adhesion of water droplets, etc., and converts them into data.

Each component of the circuits (10) to (60) including the circuit (11) is supplied with a control signal or a timing signal as necessary. These signals are generated by multiplying the output of the 7-point sensor array (95) (see also Figure 1) by n times using a frequency doubling circuit (98), which generates a signal in the swinging direction of the vibrating mirror (89) and a grating signal. It is created by performing appropriate frequency division etc. based on the signal (reference clock signal).

On the other hand, a computer system (70) is used in conjunction with this system of equipment. computer system (70)
For example, CPU constituting a microprocessor
(71) as the control main body, and includes an input/output interface 7ace l10 (72), a main memory device (73), a CRT monitor device (75), a printer device (76), etc.
They are interconnected via a bus (77).

The CPU (71) is connected to the input/output interface 7 ace l10 (
When a signal is sent to the transport system controller (80) via the transport system controller (80), the transport system controller (80) c.
The entire transport system including the transport stage (81) shown in the figure is controlled. In addition, the CPU (71)
Control is performed to write the defect data obtained by this signal processing system into the main memory device (73) via the Ace I 10 (72). The data stored in the main memory device (73) is read out as necessary and sent to the CRT monitor device (75) through operations such as a keyboard (not shown) to display the status of defect distribution, and The information is sent to a printer device (76) and printed.

Now, the analog voltage signal (So) output from the photoelectric signal output circuit (1) is sent to a high-speed A/D converter (11
) is converted into a digital signal (Sed). This digital signal (Sod) is input to an averaging circuit block (10) that sequentially averages the signals in the main scanning direction and then in the sub-scanning direction.

The main scanning line data adding and averaging circuit (12) samples the signal of one line at a period corresponding to 25 μl, and calculates the average of the two times in the sampling order, and calculates the average of the two times in the sampling order.
Processing is performed to obtain a 1-unit signal corresponding to mφ. The line signal (Sl) averaged in the main scanning direction is input to the next sub-scanning line data adding and averaging circuit (13), and this circuit allows the same signal on two main scanning lines adjacent in the sub-scanning direction to be 1 unit signals at the scanning position are added together, and 2
A new 1-unit signal is created by averaging over the scans.

Through these two averaging processes, the digital signal (S2)
Compared to the original signal (S od), the random noise component is reduced to about 1/1T=1/2.

In addition to suppressing random noise, the averaging circuit (10) has another purpose of preventing defects from being overlooked. That is, since the luminous flux of the laser beam forms a 0us distribution, the signal may vary in magnitude depending on which part of the beam spot is irradiated onto the defective portion, and may not be detected as a signal. In order to prevent this detection omission, the beam spot is scanned in the main scanning direction while passing through the defective part.

Sampling is performed twice in both the sub-scanning directions, and the average is taken.

To explain it more specifically using Figure 110, the beam spot diameter is 50 μm thick, so we are trying to obtain signals at 50 μm intervals as one unit, but the beam spot is 50 μm thick.
When sampling is performed directly when moving, that is, at points b and d in Figure 10, when the position of the defect is near the valley between the beams (B1) and (B3) as shown in the figure, the defect is detected. There is a possibility that it cannot be detected as a signal. To avoid this, when the beam is centered at the zero point shown in the figure (the beam (
B2)) Perform sampling to extract large signals corresponding to the defective portion. This sampling signal is averaged with either point b or point d to obtain one unit signal every 50 μm. Similarly, in the sub-scanning direction, since the beam spots are overlapped by 25 μm as described above, by averaging the beam spots, it is possible to prevent defects in the sub-scanning direction from being overlooked. As a result of averaging, the signal component related to the defect contained in the signal (S, d) becomes smaller, but since the noise component is reduced by 1/2, the S/N ratio does not deteriorate much. Note that the specific configuration of this averaging circuit (10) will be explained in detail in FIG.

The digital signal (B2) subjected to the averaging process is subjected to shading correction by a shading correction circuit (20) in a multiplier (23) with a time delay of one line. This shading correction is performed line sequentially and independently for each line.

A 1-line delay circuit (22) serving as a 1-line buffer 7 compensates for a time delay (one line) in creating correction data in the shading correction circuit (20).

The digital signal (B2) is once converted into an analog signal (Sza) by a D/A converter (11').

This analog signal (82a) is converted into a digital signal (X) again by an A/D converter (25) after high frequency components are removed by a nonlinear low-pass filter (LPF) (24) that does not cause time delay. . Digital signal (X)
is input to a circuit (26) that calculates the minimum value from the signal (X) for one line, and the minimum value (Xmin) is calculated. The minimum value (Xmin) is held in a holding circuit (26').

On the other hand, the digital signal (X) is transmitted through a 1-line delay circuit (2
7) gives a time delay of one line and is input to the 17X calculation circuit (28). 1/Xi-output circuit (28
) calculates a digital signal (1/X) corresponding to the reciprocal of the digital signal (X).

In the multiplier (29), the minimum value signal (XUain
) and the digital signal (1/X) of this reciprocal are synchronously multiplied. The multiplied shading correction data (X+sin/X) is output to the multiplier (23) and multiplied by the output digital signal (B2) with a time delay of exactly one line. Multiplication result signal (XIll
in/X)・(Sz), the underground level is approximately linearized, as shown in the waveform diagram of FIG.
A pulse-like signal appears on top of that level. Note that the circuit block (20) that creates data for shading correction and performs shading correction will be explained in more detail with reference to FIG.

Regarding the averaging circuit (10) and this shading correction circuit (20), if both of these circuit blocks are applied, usually the shading correction circuit (20)
A configuration is adopted in which an averaging circuit (10) is connected at a subsequent stage.

That is, the output (So) of the signal amplifier (3) is nonlinearly
, F (24), from which data for shading correction is created, and in the multiplier (23), the A/D conversion output (S, d) is inputted to the A/D conversion output (S, d) with a time delay of one line.
The configuration is such that it is multiplied by a D-converted signal (S, d), and the multiplication result is input to an averaging circuit (10) to perform averaging processing.

However, in this way, for a given scanning speed,
High speed processing in the shading correction circuit (20) is also required. In order to perform high-speed signal processing, suitable circuit elements are required, and it can also be pointed out that there is complexity in designing logic circuits such as timing control. In this respect, if the configuration is such that shading correction is performed based on the averaged signal (data) (S2) as in this embodiment, the speed is 1/2 that of the opposite configuration, and the shading correction It is possible to provide sufficient margin for processing speed.

Further, since high-speed circuit elements are not required, it is advantageous in terms of cost and design complexity can be largely eliminated. Furthermore, preferably, since data for shading correction is created from the averaged signal, (X)
The minimum value (Xa+
in) is stabilized, making signal processing easier.

The shading-corrected signal (S,) output from the multiplier (23) is sent to the circuit (S,) in order to extract the defective signal.
30) and is branched and input to the circuit (40).

The circuit (30) creates a floating base signal from the signal (S:l). That is, first, the digital signal (S,) is D/A
It is converted into an analog signal by a converter (31). Next, the analog signal is input to a nonlinear low-pass filter (32) that hardly causes any time delay, and high frequency components are removed. Then, it is input to the A/D converter (33), converted into a digital signal again, and used as a floating base signal (S,) for signal comparison by three adders (41), ( 42).

(43) respectively.

The adder (41) adds a constant level value (Ll) preset in the addition value setting circuit (44) to this floating base signal (S,), and compares it as a new floating base signal (S5). Output to the circuit (45). Above addition value setting circuit (
The level value (Ll) set in 44) is, for example, the 13th
As shown in the waveform diagram in the figure, good results can be obtained by setting the value to a value that exceeds the maximum value of the noise component of the signal (S,).

In the adder (42), a constant level value (preset in the addition value setting circuit (46)) is added to the floating base signal (S4).
L2) is added (L2>Ll; see FIG. 13) and output to the comparator circuit (47) as a new floating base signal (S6). Similarly, the adder (43) receives the floating base signal (S
, ) and a constant level value (L3) set in advance in the addition value setting circuit (48) (L3>L2; see FIG. 13), and a comparison circuit (4) as a new floating base signal (S7).
9). Note that the additional value setting circuit (44),
The respective level values (L 1 ), (L 2 ), and (L 3 ) set in (46) and (48) are determined by the CPU (
71) to the respective circuits (44) via I10 inter 71 chairs (72).

(46) and (4B).

In the comparison circuit (45), the floating base signal (S, ) and the original signal (S3) are compared. Signal (S,) > Signal (S
.
> When the signal (S6), the defect data (DFh2) is “1”
of.

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-i-% +,s,^ In the comparison circuit (49) that detects the defective signal, when the signal (S,)>signal (S7), "1" is set as the defect data (DFhs), and otherwise. 0" is output. Therefore, when (DFh,) becomes "1", data (DFh, ) (D Fhl) both become "1". Data string (DFh, ) (D Fh2
) (I) Fhl), rl 11J corresponds to the case where the defect signal exceeds the level value (L3), and when it becomes "011", the defect signal exceeds the level value (L3).
This corresponds to the case between 2) and (L3), and [ooIJ
When it becomes, it corresponds to the case where the level is between (L2) and (Ll). When it becomes "000", it corresponds to the noise level, that is, the case of no defect with no defect signal.

By setting a plurality of levels in this way, the magnitude of the defect signal can be determined, and the size of the defective portion on the inspection surface can be detected. In addition, the level value (L 1
), (L 2 ), and (L 3 ) can be arbitrarily changed by the CPU (71), so the detection sensitivity can be adjusted according to the surface condition of the specimen.

Regarding the circuit block (40) and the circuit (60), apart from the above embodiment, the configuration of the circuit block (40) is reduced to 1/3.
There have been attempts to do so. That is, instead of setting three levels, only one level is set, it is determined whether this level is exceeded or not, the number of defective signals exceeding the level is counted, and the unit section area (6a) (see Fig. 4) is determined. ) as defective data.

However, as you can see from the discussion below, the above method of using the number of defects in a unit area as defect data is
It has been pointed out that although the average density of defects is known, it is not sufficient to determine the size of the defects (for example, the size of attached dust) and their spread.

For example, as shown in FIG. 9(a), there is essentially one defect, but the average density is 11.
The result is 11%, which is the same result as when there are 11 discrete minute defects, as shown in FIG. In this respect, as in this embodiment, by setting three types of levels and determining which level the defect signal is at, the size of the defect and the density in a practical sense can be determined. There are Kirutoshi and Hiroshi.

Output data (DFh,) of the comparison circuits (45), (47), (49).

(D Fh2)-(D Fhz) is input to the 10-line defective data OR-circuit (60). This OR circuit (
60), the 3-bit defect data assigned to the minimum detection unit of 50 μm x 50 μm is logically summed for 10 defects in the main scanning direction and then for 10 lines in the sub-scanning direction, and the data is placed in the unit area (6a) shown in FIG. On the other hand, processing is performed to represent the defect data with the largest data value. The processed 10 lines of data (Dh) are sent to the CPU (71
) is sent via the I10 interface (72) to the main memory device (73) and stored therein. The 10-line defective data OR circuit (60) will be explained in more detail with reference to FIG.

Next, a circuit (50) that detects a low frequency defect signal and converts it into data will be described.

High frequency components of the photoelectric output signal (So) are removed by a nonlinear low-pass filter (51) that does not cause time delay. The output of the nonlinear low-pass filter (51) is converted into a dinotal signal by an A/D converter (52) and input to a main scanning line data averaging circuit (53). The circuit (53) sequentially averages the input signal in the main scanning direction,
Output as a signal (S+) with suppressed base level fluctuations. The signal (St) is input to the comparison circuit (54),
- It is compared with a constant level value (CI) set in the running comparison value setting circuit (55). The comparison circuit (54) has SL>
When CI, 1'' is output as the defect signal (D F +), and at other times, 0'' is output. This output is the above defect data (Dh) and the final defect data (DI
2) is passed through a DELAY circuit (59) so that the output timings are aligned. Next stage circuit (56)
integrates the defect signal (DFh) for 10 lines. The integration is performed in units of micro-section regions (6a) on the wafer surface. The integrated data (DH) is output to the next discrimination circuit (57), and is compared with the number data value (C2) set by the discrimination number setting circuit (58). By discrimination, D+,>C
If it is 2, the discrimination circuit outputs 1 bit of "1", otherwise it outputs "0".

One bit of defect data (D2) related to low frequency and three bits of defect data (Dh) related to high frequency are synchronized to I10.
interface ()2).

These data are combined into 4-bit data. 2
With zero line scans, 300 4-bit defect data are created on a 6-inch wafer. Since the computer system (70) handles data in units of 8 bits, the 4-bit defect data is combined with the data corresponding to the unit section areas (6a) adjacent in the main scanning direction to make 8 bits. Therefore, when 20 line scans are completed, 10
150 pieces of defect data of 1 byte (8 bits) are created corresponding to a line (0.5 mm width and 150 a+m length). Note that the circuit (50) will be explained in more detail in FIG. 16.

Next, circuit blocks (10), (20), circuit (60)
and the details of the circuit block (50) will be explained.

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Digital signals (S, d) are sent to two latch circuits (1
24), (This latch is sent in parallel to 12[3) at a timing synchronized with the clock obtained by dividing the clock from the sampling clock generation circuit (122) by 1/2 by the 1/2 frequency divider circuit (123). Circuit (124), (126
)i,: held alternately by the function of the knot circuit (125). The outputs of the latch circuits (124) and (126) are added by an adder (127), and the added data is shifted by 1 bit to the lower order by a circuit (128) to perform a 1/2 operation.

Averaged data in the main scanning direction (S
l) is stored in a RAM (132) capable of storing one line of data via a data selector (135), or directly input to an adder (137). Assuming that the signal (Sl) is now being written to the RAM (132), when writing for one line is completed and the next line scanning signal (St) is output from the circuit (128),
This signal (S,) is input to an adder (137). The previously written line scanning signal (S,) is then read out from the RAM (132) via the data selector (135) and synchronously input to the adder (137).

The respective signals (S,) of the previous and current line scans are:
Add with adder (137)! X, is, average circuit (13B)
1 bit is shifted to the lower order and 1/2 operation is performed, and the averaged signal (S
2) is output. Note that (130) is a counter that inputs a clock obtained by dividing the sampling clock by 1/2, and serves as an address counter that provides an address signal to the RAM (132).

The data selector (135) controls switching of the data bus of the RAM (132).

Furthermore, in FIG. 11, the scanning direction signal generation circuit (129
) outputs a scanning direction signal (SYNC) whose logic signal level is alternately switched in accordance with the scanning direction of the laser beam. Each clock for the processing circuit uses this scanning direction signal (
SYNC) is generated only when the signal level is the same, so that data is output only when the laser beam is scanned in the same direction. In addition, the sub-scanning direction 1/2 circuit (1
39) allows the clock from the circuit (123) to pass only when scanning one line in two reciprocating scans of the laser beam, and
A clock (CK) and a clock (SCK) are generated to operate the circuits (30), (40), (50) and (60) shown in the figure.

In FIG. 12 showing details of the circuit block (20),
The digital signal (
X) is a latch circuit (261), (26°) and a comparator (
262) and two RAMs each storing one line of digital signals.
(271) and (272) are sent in parallel to the memory section (27). Now, when writing to the RAM (271), an address is input from the write counter (273) to the RAM (271) via the address selector (275), and the latched digital signal (X ) are written sequentially. At the same time, the comparator (262) compares the sequentially input digital signal (X) with the output from the latch circuit (261), and only when the signal (X) is small, the comparator (262)
A capture signal is given to the latch circuit (261), and the digital signal (X) at that time is latched. The initial value of the latch circuit (261) is, for example, "FF".

The minimum value (Xn+in) is found at (261) and transferred to the latch circuit (26') using a predetermined timing signal. Thereafter, the latch circuit (261) again latches the initial value rFFJ for determining the minimum value for the next line signal.

On the other hand, at the stage when this minimum value (Xmin) is found, RA
A signal for one line is written in M (271).

Next, a read counter (27) is stored in the RAM (271).
The read address is supplied from 4) via the address selector (275), and the read digital signal (
X) is input to the latch circuit (281) of the 1/X calculation circuit (28) via the data selector (279).

ROM (282) row input (X) as address, (1
/X) and outputs a digital signal (1/X) according to the input from the latch circuit (281). Multiplier (2
9), the digital signal (1/X) that is sequentially output
is multiplied by the minimum value (Xmin) from the latch circuit (26').

The signal read from the RAM (271) is
r7! NFJam a h f L,% 7. Cabinet-L
The next line signal is written into A-tl'+ RAM (172). That is, write counter (2
73) through the address selector (276)
A write address is given to M (272), and the digital signal (X) from the latch circuit (251) is written via buffer r (278).

When the multiplier (29) finishes processing one line of signals, the latch circuit (26') has already determined the minimum value for the next line, and the selectors (275) and (276)
, (279) are switched to perform the arithmetic processing of the next line. Such switching operations are repeated alternately to create shading correction data (Xmin/X) independently for each line.

Correction data (Xmin/X) from multiplier (29)
is input to the multiplier (23) via the latch (291), and on the other hand, the digital signal (S2) from the delay circuit (22) is also input to the multiplier (23) via the latch (221).
) is entered.

The output of the multiplier (23) is then output as a shading-corrected signal (S,) to the next stage circuit via the latch (231).

The automatic shading correction value generation circuit as described above can be applied not only to this signal processing system but also to general processing systems that require shading correction. In other words, a spot light source such as a laser beam performs a rask scan operation on a sheet-shaped object, or the object is uniformly illuminated and the scattered, reflected, or transmitted light is emitted from the object. It has a function to detect as a voltage signal in the line direction, the reference value of the detection voltage changes over time, and it has a method to process the pulse-like signal on the signal voltage from a certain effective width in each line direction as an effective signal. Available about equipment.

Conventionally, in signal correction such as shading correction, the method of collecting the data necessary for correction is to use a reference object that does not generate an effective signal, calculate the signal value, its maximum and minimum value as a calibration in advance, and correct it to the inspection data. Generally, the sensitivity of the photoelectric converter is changed by directly measuring the amount of light from the light source or by measuring the average value of the detected voltage. However, when the reference object required to collect the data necessary for calibration is used, such as when the effective signal is scattered light from an object of submicron size, it is a practical problem that there are no defects or dust of that size. It is nearly impossible to obtain a reference that does not exist. Furthermore, when the effective signal voltage is weak compared to the change in the reference value of the signal voltage, various difficulties are encountered in either method.

In particular, it can be pointed out that with the method of correcting the sensitivity of the photodetector, it is not possible to follow up in terms of speed.

The above-mentioned circuit calculates correction data directly and sequentially from the inspected object, applies shading correction to each scan line independently, and outputs the corrected data with a certain time delay. can be resolved.

In other words, according to this circuit, correction signals can be obtained sequentially while maintaining a time delay of one line without any time loss due to calibration, etc., so processing equivalent to 1J full time is possible, and it is possible to process signals that vary considerably. It also has the effect of stably correcting.

Next, details of the circuit (60) will be explained with reference to the fjS14 diagram.

Defect data (D Fh,) (D Fh2) (D Fh,
) is temporarily held in the buffer y (613).

From the buffer (613), these three
Bit data is output to the OR circuit (614). On the other hand, the data read from the RAM (611) or the RAM (612) is latched in the latch circuit (615), and the output data and the data from the buffer y (613) are latched in the OR circuit (614). ), the logical OR is performed for each bit.

The 3-bit data output from the OR circuit (614) is once held in the latch circuit (StS) and then read out via either the bidirectional buffer (616) or (617). RAM (611) or (
612) at the same address. RAM (61
1) and RAM (612) each have 300 addresses and each form defective data for 10 lines. When data for 10 lines is formed in one RAM (611), it is switched to RAM (612), and defective data for the next 10 lines is sequentially formed in RAM (612). When the logical sum data is updated one after another in this RAM (612), the RAM (612)
11), the formed defect data (Dh) is read out via the data selector (819), and is read out from I.
10 interface (72).

To simplify the operating principle of the OR circuit (614) and explain it with reference to FIG. Assume that 300 pieces of data obtained by performing OR processing for 10 units are stored for the first line. The switch (swi) and the switch (SW2) are switched in conjunction with each other, and if the switch (SWI) is now switched to the read side of the RAM (M), data specified by a certain address will be read and latched. (L).

Here, the held data and the data of one unit (the number of main scanning samplings) of a large line are logically summed in an OR circuit (OR). At this time, the switch (SW2) is switched to the write side, and this logical sum data is written to the same address, and this is repeated 10 times in the main scanning sampling number (see FIG. 4).

Next, the address is incremented by 1, the next 10 units of OR data are read out, the next 1 unit of data is logically ORed, the switch (SW2) is reversed to the write side, and this increment is performed. Write the result of the logical OR processing to the same address. This operation is repeated for 10 units. After the OR processing in the main scanning direction is completed, similar processing is performed on the data for the sub-scanning direction, that is, the remaining lines.

Next, the details of the circuit block (50) will be explained with reference to FIG.

Pulsed high frequency components of the photoelectric output signal (So) are removed by, for example, a 200 KHz nonlinear low-pass filter (51). The output of the nonlinear low-pass filter (51) is, for example, a 450 KHz A/D converter (52).
For example, every other scan of 20 scans is converted into a digital signal by (this is because defect signals related to low frequencies do not necessarily require averaging in the sub-scanning direction). The digital signal is input to an averaging circuit (53) in the main scanning direction. This circuit (53) is
This circuit is similar to the circuit (21) shown in FIG. , is input to the comparator (54) as a signal (S+). A constant level value signal (C9) is input to the comparator (54) as a comparison input from the buffer T (55) to which a comparison setting value has been set via the unit 10 (72). The comparator (54) outputs "1" as the defect signal (DF+) when S t>C+. In addition, the above buffer
y (55), a constant level value signal (CI) is given, but the beam flux at the wafer surface (
For example, a comparison value can be provided in synchronization with the comparison signal (S[) so as to form a bow-shaped distribution in the main scanning direction, in association with a change in the amount of light in the main scanning direction (main scanning direction). However, as shown in Figure 1, the beam flux is configured to be incident almost perpendicularly over the scanning width on the surface of the 9-bar surface (6s), so the change in light intensity is extremely small, and even if the beam is a constant level value signal (C5), there is no problem.

The output (DFL) from the comparator (54) via the DELAY circuit (59) is added to the output from the latch circuit (565) by an adder (584). As mentioned above, the DELAV circuit (59) receives defect data (
It is used to match the timing with Dh).

The signal (DFL) has 300 "1"s per line.

“On”.This is connected to 1 by the circuit (56).
Integrate 0 lines (RAM (561) or RAM (5
62), number data of O to 10 is accumulated in one address). The mode of integration is generally the same as that explained in FIG. 14, and the OR circuit (614) can be replaced with an adder (564).
The explanation of the function 9) will be omitted.

The output data (Dh) of the data selector (569) is compared with the data (C2) set in the discrimination number setting circuit (58) by the comparator (57). The comparator (57) is
When D + r > C2, "1" is output to D12, and otherwise, "0" is output to DL2. The 1-bit data (D12) is sent to l10 (72) and is combined with the 3-bit data (Db) related to the high frequency.

In addition, as in the above circuit, before digitizing the photoelectric output signal (So), by separating and extracting the low-frequency defects caused by clouds on the wafer using a low-pass filter, the results shown in Figure tjIJ7 are obtained. The configuration of the signal processing system shown is simplified, and the manufacturing cost is also reduced.

That is, in conventional defect inspection equipment, in order to distinguish between clouds, smudges, etc. and minute defects on a wafer or mask, the photoelectric output signal is A/D converted and then judged based on the difference in signal level from the surrounding signal level. However, there is a problem in that a large number of digital buffers T and arithmetic circuits are required to identify the signals, and the arithmetic processing is also complicated. In this embodiment, this problem is solved by separating into two systems before digitization.

Next, a method of outputting the obtained defect data will be explained.

In FIG. 7, the defect data obtained in the circuit (60) and the circuit (57) are stored in l1 under the control of the CPU (71).
0 (72) and stored in the memory device (73).

The problem is how to output this stored data as information. In this example, a color CRT is used for the CRT monitor (75) to improve efficiency in identifying defective states.

Before showing a specific example, first, a general method for outputting data existing in memory as visualization information to, for example, a CRT monitor will be described.

Data stored in memory is visualized as information as needed. Visualization can be roughly divided into two methods: printing it on paper and displaying it on a monitor. The former method has the advantage that all data on the memory can be output, but apart from graphic recording, it has the disadvantage that it is difficult to intuitively understand the meaning of the data, such as in the case of printed recording.

On the other hand, the latter method is preferable because it allows numerical data, etc. to be displayed in a pattern, and the meaning of the data can be grasped intuitively and easily, but on the other hand, it is constrained by the screen size, and the amount of information that can be displayed is limited. It has the disadvantage of being damaged.

As described in this specification, in semiconductor manufacturing processes, defect inspections of wafers and masks are performed with extremely high precision using automatic inspection equipment.

During these inspections, the amount of data collected is enormous, and each piece of data carries positional data corresponding to the inspection location. When visualizing such data as information, in addition to a print printer, it has been common to use a black and white CRT monitor for ease of grasping defect conditions. Defects can be expressed as binary data (defects present/absent), and the data is binary data, but due to screen size restrictions related to CRTs, it is impossible to display all data in patterns at once on a black and white CRT. . Therefore, usually C
The inspection area of the object to be inspected is roughly divided vertically and horizontally within the number of displayable pixels in the vertical and horizontal directions of the RT, and the state of defects in the divided small areas is displayed in a pattern. For example, if there is a maximum defect within a sub-region, the corresponding pixel (or dot) will be displayed as "white" (if there is no defect, it will be displayed as "black"), or if there is even one defect within the sub-region, the corresponding pixel (or dot) will be displayed as "white". If so, the corresponding pixel is displayed as "white".

However, this conventional method has the disadvantage that it is difficult to accurately grasp the defect situation. In other words, it is not possible to determine at what level the defect exists in the corresponding subarea that is displayed as "white" as having a defect. In addition, in the case of wafers, etc., there are discrete defects such as scratches and dust,
It may be difficult to distinguish between defects that are uniformly distributed such as clouds and clouds.

Therefore, it is necessary to solve this inconvenience, that is, the fact that even if data is displayed in patterns on a black and white monitor, the original meaning of all data cannot be faithfully visualized.
In other words, all collected data can be displayed as information on a monitor with limited display size without losing its original meaning, so that the overall picture of the data can be accurately grasped. was set as an issue.

To solve this problem, a color CRT was used to display the defect level in different colors, making it possible to accurately grasp the status of defect distribution. It should be noted that the present invention can be applied not only to color CRTs but also to color monitor shells using liquid crystals, etc., and can also be applied to purposes other than defect inspection.

Therefore, if we treat it as a technical concept, when a quantity of level data is determined as a function of two-dimensional position data and that level data is output as visualization information, a color monitor is used, and the two-dimensional position data is This information output method is characterized in that the level data is made to correspond to the dot position of the dot position, and the level data is made to correspond to different colors depending on the class a, and the level data is displayed for each color on a color monitor.

To explain the above-mentioned embodiment, first, as shown in FIG.
Each pixel (or dot) of 00 has a 300x300 micro-section area (6a) on the wafer surface (6S) shown in FIG.
Match each of them. Then, this micro-compartment area (
The defect level information in step 6a), that is, the defect data stored in the memory device (73), is made to correspond to different colors depending on the type, and is displayed as a map on the color CRT (75). This control is performed by a computer system (70)
It is controlled by the CPU ( ) 1) and executed by a program.

One aspect of the control is shown in a 70-chart in FIG. 17.

Here, to explain the main steps related to display in the 70-chart of FIG. 17, step (SPloo)
In step (SP102), the 10 line scanning completion signal is detected from the circuits (56) and (60), and the data (D12) is output from the circuit (57) and the circuit (60).
, (Dh) and input this data to step (SP1
03), the data is converted into color data for monitor use. Then, in step (SPI04), this color data is written into the monitor memory area (X, Y) for CRT.

As a result, in step (SP105),
As shown in FIG. 5, the position, size, and level of the defect are displayed in color on the CRT monitor (75).

The above operation is repeated for 300 X addresses. Similar operations are then repeated for successive Y addresses.

For example, if the defect is "111", it is marked as "red" JJO11J, "orange JJOOIJ" is marked as "blue" or "black" (no display) as there is no defect in green JJO00J. Note that 1-bit data corresponding to a distributed defect has priority over level data, and if that bit of the 1/2-byte data is "1", it is unconditionally displayed as a "white" dot, and a distributed defect is It can be clarified that

In addition, in FIG. 7, the circuit (10) is replaced by the circuit (11).

Although the circuit (11°) is inserted between the circuit (22), the circuit (11°) is omitted from the circuit configuration shown in Fig. 7, and the output signal (So) of the signal amplifier (3) is nonlinearly converted to P, F (24). input,
The output of the A/D conversion circuit (11) is input to the 1-line DELAY circuit (22), and the output of the circuit (20) is input to the circuit (1).
The output of the circuit (10) may be used as the input of the circuit (31) and the input of the circuit (40).

FIG. 18 shows an overall block diagram of a signal processing system according to another embodiment of the present invention configured as described above.

As is clear from the above explanation, according to the present invention, although the weak scattered light at the surface defect is directly detected, the weak signal is basically processed digitally. Therefore, the signal processing is stabilized, and the above-mentioned minute signal is efficiently separated from the noise component, and shading correction is performed independently of the scanning line in real time, etc., so that the signal processing is stabilized. The processing accuracy is improved, and it is possible to detect defects on the submicron order. By the way, the device according to this invention can detect 0 defects.
．． It is possible to import up to 5μφ.

According to another invention, distributed defects are separated and extracted at an early stage by passing the analog signal from the photoelectric signal output means through a low-pass filter. This has the effect of simplifying the overall configuration compared to conventional circuits that are designed to detect defects in combination with defects, and also facilitates the processing of defect data.

In addition, according to the embodiment of the present invention, since the scattered light is effectively and efficiently focused over the scanning width using the cylindrical lens, high precision circuits are not required for each element of the signal processing system. There are advantages.

Furthermore, since the efficiency of charging conversion is improved by using an optical fiber bundle and a photomultiplier tube, it is advantageous in terms of the magnitude of the photoelectric signal and the time response compared to the signal processing system.

Furthermore, the first signal processing means, that is, the circuit that averages signals in the main scanning direction and the sub-scanning direction, samples and averages at intervals smaller than the sampling time corresponding to the beam spot diameter. , failure to detect defective locations can be prevented.

In addition, we have developed a system in which the defect signal is used as defect data by determining the existence state of each minute area on the surface of the test object on the hardware side, and by sequentially switching the RAM. By adopting this method, there are advantages in that the capacity of a memory device in which defective data is to be stored can be significantly reduced, and at the same time, defective data can be easily processed. moreover,
Obtaining defect data regarding pulsed defects and distributed defects at the same time is convenient for subsequent data processing, such as recording printing and map display of defect status.

Then, the state of defects in micro-section areas on the surface of the test object, that is, the distribution state of defects and their individual sizes, is divided into low frequency and high frequency components, and the high frequency differs depending on the level of the size. By making it correspond to color and displaying the map color on the color monitor, it is now possible to quickly and accurately grasp the status of defects, making the inspection process more efficient and improving the precision of inspection. This can contribute to improving product yield.

[Brief explanation of the drawing]

Fig. 1 is a perspective view of an optical system according to an embodiment of the present invention, Fig. 2 is an explanatory diagram showing the relationship between a 6-inch diameter wafer and scanning as an example, and Fig. 3 is an illustration of the laser beam scanning of this embodiment. A schematic explanatory diagram; FIG. 4 is an explanatory diagram showing the state of defects corresponding to divided minute regions on a wafer; FIG. 5 is a diagram schematically showing the screen of a CRT monitor; FIG. 6 (a); (b) is a waveform diagram showing each of the signals processed individually in two systems, FIG. 7 is an overall block diagram of the signal processing system according to an embodiment of the present invention, and FIG. 8 is a waveform diagram of the signal after shading correction. A waveform diagram showing an example; Figures 9(a) and (b) are diagrams for explaining the difficulties of the attempted defect counting method; Figure 10 relates the processing in the averaging circuit (10) to the scanning beam. FIG. 11 is a block circuit diagram showing details of the averaging circuit (10), FIG. 12 is a block circuit diagram showing details of the shading correction circuit (20), and FIG. 13 is a block circuit diagram showing details of the shading correction circuit (20). FIG. 14 is a waveform diagram for explaining how defective signals are determined according to their levels.
0), Fig. 15 is an explanatory diagram showing the principle of storing defective data in RAM memory, Fig. 16 is a circuit diagram for detecting a defective signal related to low frequency, Fig. 17 is a color diagram. FIG. 18 is a signal processing diagram according to another embodiment of the present invention in which the circuit configuration of FIG. 7 is partially modified. FIG. 2 is an overall block diagram of the system. 1... Photoelectric signal output circuit, 11... A/D converter,
10... Signal averaging circuit, 20... Shading correction circuit, 30. 40... High frequency defect signal extraction circuit, 50... Extracting a low frequency defect signal and converting it into data. Circuit, 60... Defect data/OR circuit for obtaining defect data related to high frequency according to unit areas obtained by minutely dividing the surface of the object to be inspected, 70... Computer system, 81... Transport stage, 82...・Laser beam scanning means. Patent applicant Dainippon Screen Manufacturing Co., Ltd. #lI! Person Patent Attorney + Osamu Satkawa + Iil Shukasaya C Figure 4 Figure 9 C) a), - w & law

Claims (8)

[Claims] (1) a photoelectric signal output means for outputting an electric signal according to the intensity of light diffusely reflected by a defective part on the surface of the object to be inspected scanned by the laser beam; and converting the output signal of the photoelectric signal output means from analog to digital; A first signal processing means that sequentially performs signal averaging processing on the digital signal in the main scanning direction and then in the sub-scanning direction to suppress noise components; and shading based on the output of the first signal processing means. a second signal processing means that creates correction data and performs shading correction on the output of the first signal processing means in real time; and a signal processing means that removes high frequency components from the output of the second signal processing means. A circuit for providing a base signal for comparison, a plurality of adder circuits for adding a plurality of preset different level signals to the base signal, and an output of each of the adder circuits and an output of the second signal processing means. A surface defect inspection apparatus comprising: a third signal processing means having a comparison circuit that compares the signals and outputs defect signals related to high frequencies as defect data according to the magnitudes of the signals. (2) a photoelectric signal output means for outputting an electric signal according to the intensity of the light diffusely reflected by the defective part of the surface of the test object scanned by the laser beam; and converting the output signal of the photoelectric signal output means from analog to digital; a second signal processing means that performs shading correction in real time; and averaging processing of signals is sequentially applied to the output of the second signal processing means in the main scanning direction and then in the sub-scanning direction to suppress noise components. a first signal processing means; a circuit for removing high frequency components from the output of the first signal processing means to provide a base signal for signal comparison; and a circuit for providing a base signal for signal comparison; A plurality of adder circuits are added, and the output of each of the adder circuits is compared with the output of the second signal processing means, and defective signals related to high frequencies are output as defective data depending on the magnitude of the signal. A surface defect inspection device comprising: a third signal processing means having a comparison circuit. (3) a photoelectric signal output means for outputting an electric signal according to the intensity of the light diffusely reflected by the defective part of the surface of the object scanned by the laser beam; and converting the output signal of the photoelectric signal output means from analog to digital; A first signal processing means that sequentially performs signal averaging processing on the digital signal in the main scanning direction and then in the sub-scanning direction to suppress noise components; and shading based on the output of the first signal processing means. a second signal processing means that creates correction data and performs shading correction on the output of the first signal processing means in real time; and a signal processing means that removes high frequency components from the output of the second signal processing means. A circuit that provides a base signal for comparison, a plurality of adder circuits that add a plurality of preset different level signals to the base signal, the output of each of the adder circuits, and the output of the second signal processing means. a third signal processing means having a comparison circuit for comparing the high frequency defect signals and outputting the defect signals as defect data according to the magnitude of the signals; a circuit for extracting components; a signal averaging circuit for suppressing fluctuations in the base level by sequentially averaging the output of this circuit in the main scanning direction; and a comparison circuit for detecting a defect signal corresponding to a defect distributed on the surface of the test object and outputting defect data related to low frequency by comparing the level signal with the level signal of the test object. A surface defect inspection device characterized by comprising: (4) The third signal processing means has a circuit that represents a unit area obtained by minutely dividing the surface of the test object with defect data corresponding to the largest defect signal related to high frequency; The signal processing means integrates the defect data outputted from the comparison circuit provided here in correspondence to the micro-section unit area, and compares it with preset number data to identify defects corresponding to the unit area related to low frequency. It has a comparison/discrimination circuit that outputs data, and combines the representative high-frequency defect data and the low-frequency defect data corresponding to the unit area to form one defect unit data for the micro-section unit area. A surface defect inspection device according to claim (3). (5) At least, the defect data related to high frequency is made to correspond to different colors depending on the type of data, and the color monitor further comprises means for displaying the level of the defect size in different colors. ) The surface defect inspection device described in item 2. (6) a photoelectric signal output means for outputting an electric signal according to the intensity of the light diffusely reflected by the defective part of the surface of the test object scanned by the laser beam; and converting the output signal of the photoelectric signal output means from analog to digital; a second signal processing means that performs shading correction in real time; and averaging processing of signals is sequentially applied to the output of the second signal processing means in the main scanning direction and then in the sub-scanning direction to suppress noise components. a first signal processing means; a circuit for removing high frequency components from the output of the first signal processing means and providing a base signal for signal comparison; and a plurality of different level signals set in advance for the base signal. A plurality of adder circuits for adding a plurality of adder circuits compare the outputs of each of the adder circuits and the output of the second signal processing means, and output defective signals related to high frequencies as defective data according to the magnitude of the signals. a circuit for extracting low frequency components from the output signal of the photoelectric signal output means; and a signal processing means for sequentially averaging the outputs of the circuit in the main scanning direction. A signal averaging circuit suppresses level fluctuations, and the output of this signal averaging circuit is compared with a predetermined level signal, and defects corresponding to defects distributedly present on the surface of the test object are detected. A surface defect inspection apparatus comprising: a fourth signal processing means having a comparison circuit that detects a signal and outputs defect data related to low frequencies. (7) The third signal processing means has a circuit that represents a unit area obtained by minutely dividing the surface of the object with defect data corresponding to the largest defect signal related to high frequency; The signal processing means integrates the defect data outputted from the comparison circuit provided here in correspondence to the micro-section unit area, and compares it with preset number data to determine the defects corresponding to the unit area related to low frequency. It has a comparison/discrimination circuit that outputs data, and combines the representative high-frequency defect data and the low-frequency defect data corresponding to the unit area to form one defect unit data for the micro-section unit area. A surface defect inspection device according to claim (6). (8) At least, the defect data related to high frequency is made to correspond to different colors depending on the type of data, and the color monitor further comprises means for displaying the level of the defect size in different colors. ) The surface defect inspection device described in item 2.