JPS62111196U - - Google Patents
Info
- Publication number
- JPS62111196U JPS62111196U JP20461985U JP20461985U JPS62111196U JP S62111196 U JPS62111196 U JP S62111196U JP 20461985 U JP20461985 U JP 20461985U JP 20461985 U JP20461985 U JP 20461985U JP S62111196 U JPS62111196 U JP S62111196U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- electrode terminal
- terminal portions
- cover glass
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims description 8
- 239000006059 cover glass Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 2
- 230000001070 adhesive effect Effects 0.000 claims description 2
- 239000010408 film Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 description 2
Landscapes
- Electroluminescent Light Sources (AREA)
Description
第１図は本考案に係る薄膜ＥＬパネルの一実施
例を示す一部省略部分を含む平面図、第２図は第
１図のＴ１―Ｔ１線に沿う拡大断面図、第３図は
第２図のＴ２―Ｔ２線に沿う部分断面図、第４図
乃至第８図は第１図のパネルの製造工程を説明す
るためのもので、第４図は基板の部分平面図、第
５図は第４図のＴ３―Ｔ３線に沿う拡大断面図、
第６図乃至第８図は各製造工程での基板断面図で
ある。第９図は本考案の他の実施例を示す部分断
面図、第１０図は第９図のＴ４―Ｔ４線に沿う部
分断面図である。第１１図は従来の薄膜ＥＬパネ
ルの一部省略部分を含む平面図、第１２図は第１
１図のパネルの拡大断面図で、左半分はＸ方向の
断面図、右半分はＹ方向の断面図、第１３図は第
１１図のパネルの周縁部の拡大断面図である。
１……基板、２……ＥＬ素子、３，７……電極
、ｍ，ｎ……電極端子部、８……カバーガラス、
９……接着剤、１３，１６……絶縁膜、Ａ……カ
バーガラス固着予定部分。
FIG. 1 is a plan view with some omitted parts showing an embodiment of the thin film EL panel according to the present invention, FIG. 2 is an enlarged sectional view taken along the line T 1 - T 1 in FIG. 1, and FIG. FIG. 2 is a partial cross-sectional view taken along the line T 2 - T 2 , FIGS. 4 to 8 are for explaining the manufacturing process of the panel shown in FIG. 1, and FIG. 4 is a partial plan view of the substrate; Figure 5 is an enlarged sectional view taken along line T 3 - T 3 in Figure 4;
6 to 8 are cross-sectional views of the substrate at each manufacturing process. FIG. 9 is a partial sectional view showing another embodiment of the present invention, and FIG. 10 is a partial sectional view taken along line T 4 -T 4 in FIG. 9. Fig. 11 is a plan view of a conventional thin-film EL panel with some parts omitted, and Fig. 12 is a plan view of a conventional thin film EL panel.
1 is an enlarged sectional view of the panel in FIG. 1, the left half is a sectional view in the X direction, the right half is a sectional view in the Y direction, and FIG. 13 is an enlarged sectional view of the periphery of the panel in FIG. 11. 1... Substrate, 2... EL element, 3, 7... Electrode, m, n... Electrode terminal portion, 8... Cover glass,
9... Adhesive, 13, 16... Insulating film, A... Portion to be fixed to cover glass.
Claims (1)
極の、前記基板の周縁部上に延設された外部引出
し用電極端子部上に横切らせて、絶縁性接着剤を
介してカバーガラスを固着したものにおいて、 前記基板周縁部のカバーガラス固着予定部分の
少なくともＥＬ素子電極端子部間に、基板と電極
端子部との段差を解消する絶縁膜を予め選択的に
被着形成したことを特徴とする薄膜ＥＬパネル。[Claims for Utility Model Registration] An insulating adhesive is applied across the external lead-out electrode terminal portions of each electrode of a matrix-type EL element formed on a substrate, extending over the peripheral edge of the substrate. In the case where the cover glass is fixed through the substrate, an insulating film is selectively applied in advance at least between the EL element electrode terminal portions of the portion of the substrate periphery where the cover glass is to be fixed, to eliminate the level difference between the substrate and the electrode terminal portions. A thin film EL panel characterized by the following:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20461985U JPH0145117Y2 (en) | 1985-12-28 | 1985-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20461985U JPH0145117Y2 (en) | 1985-12-28 | 1985-12-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62111196U true JPS62111196U (en) | 1987-07-15 |
| JPH0145117Y2 JPH0145117Y2 (en) | 1989-12-26 |
Family
ID=31170619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20461985U Expired JPH0145117Y2 (en) | 1985-12-28 | 1985-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0145117Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012063781A (en) * | 2000-03-10 | 2012-03-29 | Semiconductor Energy Lab Co Ltd | Electronic device |
-
1985
- 1985-12-28 JP JP20461985U patent/JPH0145117Y2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012063781A (en) * | 2000-03-10 | 2012-03-29 | Semiconductor Energy Lab Co Ltd | Electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0145117Y2 (en) | 1989-12-26 |
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