JPS62109245U - - Google Patents
Info
- Publication number
- JPS62109245U JPS62109245U JP19907185U JP19907185U JPS62109245U JP S62109245 U JPS62109245 U JP S62109245U JP 19907185 U JP19907185 U JP 19907185U JP 19907185 U JP19907185 U JP 19907185U JP S62109245 U JPS62109245 U JP S62109245U
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- address data
- stack area
- storing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Executing Machine-Instructions (AREA)
Description
第１図はこの考案の一実施例の回路構成を示す
ブロツク図、第２図は従来のアドレス設定回路の
一例を示すブロツク図である。
１１……ＲＯＭ、１２……ＲＯＭアドレス部、
１３，１８……ＲＡＭ、１４……インストラクシ
ヨンデコーダ、１５……演算部、１７，２０……
トランスフアゲート、２１……アドレスカウンタ
、２３，２４……ＯＲゲート。
FIG. 1 is a block diagram showing a circuit configuration of an embodiment of this invention, and FIG. 2 is a block diagram showing an example of a conventional address setting circuit. 11...ROM, 12...ROM address section,
13, 18...RAM, 14... Instruction decoder, 15... Arithmetic unit, 17, 20...
Transfer gate, 21... address counter, 23, 24... OR gate.
Claims (1)
ドレスデータに対応するプログラムを実行すると
ともにネクストアドレスデータを出力する手段と
、サブルーチンコールでのコール命令のアドレス
データを最下位から少なくとも１ビツト除いてス
タツク領域に記憶する手段と、リターン命冷によ
り上記スタツク領域のアドレスデータを読出す手
段と、この手段にて読出されたアドレスデータに
上記スタツク領域への記憶が除かれた数の所定の
データを挿入しネクストアドレスデータとして出
力する手段とを具備したことを特徴とするアドレ
ス設定回路。 means for storing a control program and outputting next address data while executing a program corresponding to address data in an address field; and storing address data of a call instruction in a subroutine call in a stack area excluding at least one bit from the lowest order. means for reading out the address data in the stack area by means of a return operation; and means for inserting a predetermined number of data, the number of which has been removed from the storage into the stack area, into the address data read by the means, and reading the next address. An address setting circuit comprising: means for outputting as data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19907185U JPS62109245U (en) | 1985-12-26 | 1985-12-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19907185U JPS62109245U (en) | 1985-12-26 | 1985-12-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109245U true JPS62109245U (en) | 1987-07-11 |
Family
ID=31160351
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19907185U Pending JPS62109245U (en) | 1985-12-26 | 1985-12-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109245U (en) |
-
1985
- 1985-12-26 JP JP19907185U patent/JPS62109245U/ja active Pending
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