JPS62108613A - Triangle wave generating circuit - Google Patents

Abstract

PURPOSE:To generate a triangle wave signal whose duty is 100% by extracting a symmetrical triangle wave and the 2nd symmetrical triangle wave being the inversion of the symmetrical triangle wave at each 180 deg.. CONSTITUTION:A transmission circuit 16 is provided, which generates a triangle wave signal VA having a prescribed period and duty and the 1st and 2nd rectangular wave signals VB, VC having an equal period to that of the said triangle wave signal and different amplitude from each other. The signals VA, VB are fed to an AND circuit 17 and fed respectively to signal inverting circuits 18, 19. Then output signals the inverse of VA, the inverse of VB from the circuits 18, 19 are fed to an AND circuit 20 and an output signal VD of the circuit 17 and an output signal VE of the circuit 20 are fed to an OR circuit 21. The output signal VF of the circuit 21 is outputted as the triangle wave signal whose duty is 100%.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to a triangular wave generation circuit used in communication equipment such as television receivers and radio receivers, and various measuring instruments, and particularly relates to a triangular wave generation circuit with a duty of 100%. It is designed so that it can be generated.

[Technical background of the invention] FIG. 4 shows an example of a conventional triangular wave generating circuit.

This triangular wave generation circuit is constructed using an operational amplifier circuit 10, and its non-inverting input terminal (+) is supplied with a voltage obtained by dividing the power supply potential Vcc by a pair of resistors 11 and 12. The signal of the output terminal is fed back through the resistor 13, and on the other hand, a capacitor 14 is inserted between the inverting input terminal (-) and the ground potential Vss, and a capacitor 14 is inserted between the inverting input terminal and the output terminal. The capacitor 14 is charged through the resistor 15, and the hti current is supplied.

FIG. 5 is a waveform diagram showing potential changes of the signals VA, VB, and VC at the inverting input terminal, non-inverting input terminal, and output terminal, respectively, in the conventional circuit. In the above conventional circuit,
When the input signal VA at the inverting input terminal is at a low potential and the input voltage VB at the non-inverting input terminal is at a high potential, the output signal VC at the output terminal is at a high potential, for example, the power supply potential. As a result, the capacitor 14 is thereafter charged via the resistor 15, and the signal potential VA gradually increases. and the potential VA
When VB reaches VB, the signal VC at the output terminal of the operational amplifier circuit 10 is inverted to a low potential, for example, ground potential.

After this inversion, the signal VB is immediately brought to a low potential via the resistor 13. Furthermore, since the capacitor 14 is discharged via the resistor 15, the potential of the signal VA gradually decreases. Then, when the potential VΔ reaches VB, the output signal VC at the output terminal of the operational amplifier circuit 10 is inverted to a high potential again. From then on, the same work will be repeated. Here, when the output current and the sink current of the operational amplifier circuit 10 are equal,
The inverting input terminal of the operational amplifier circuit 10 has a duty of 5.
A triangular wave signal VA of 0% is obtained. Further, a rectangular wave signal VB is obtained at the non-inverting input terminal, and a rectangular wave signal VC having a different amplitude from the signal VB is obtained at the output terminal.

[Problems with the Background Art] In such a triangular wave generation circuit, in order to change the duty of the triangular wave signal VA, it is necessary to adjust the current intake amount or current output amount of the operational amplifier circuit 10. The composition of the system must be changed. For this reason, the conventional circuit described above has a drawback in that it is difficult to generate a triangular wave signal with a duty of 100% as shown in the waveform diagram of FIG.

[Object of the Invention] This invention has been made in consideration of the above circumstances, and its purpose is to provide a triangular wave generation circuit that can generate a triangular wave signal with a duty of 100%. .

[Summary of the Invention] In order to achieve the above object, the present invention uses an oscillation circuit to generate a triangular wave signal having a predetermined period and duty, and a first and second triangular wave signal having the same period as the triangular wave signal and having different amplitudes. A rectangular wave signal is generated, the emitters of the first and second transistors are combined to form a first differential pair, and a triangular wave signal is applied to the bases of the first transistor and the emitters of the second transistor are connected to the base of the first transistor. A first rectangular wave signal is supplied to the bases of the i-, a constant DC current is supplied to the tenth differential pair by current source means, and the third and fourth i-
the emitter of the transistor is coupled to the collector of the first transistor to form a second differential pair; - the base of the third transistor receives the second square wave signal superimposed on a predetermined DC bias voltage; A predetermined DC bias voltage is supplied to the base of the fourth transistor, and
the emitters of the fifth and sixth transistors are coupled to the collector of the second transistor, the collector of the fifth transistor is coupled to the collector of the third transistor, and the collector of the sixth transistor is coupled to the collector of the third transistor; The transistor is coupled to the collector of the transistor to form a third differential pair, the base of the fifth transistor is supplied with a predetermined DC bias voltage, and the base of the sixth transistor is supplied with the above-mentioned DC bias voltage superimposed on the predetermined DC bias voltage. The second rectangular wave signals are respectively supplied, and one end of the load means is connected to the collector connection points of the third and fifth transistors or the collector connection points of the fourth and sixth transistors.

Next, before a detailed explanation of this invention, the principle of this invention will be explained in the seventh section.
This is done using the circuit shown in the figure. In this principle circuit, as in the conventional circuit, an operational amplifier circuit 10, resistors 11, 12, 13
and 15, a capacitor 14, and a triangular wave signal VA having a predetermined period and duty, and a first rectangular wave signal VB and a second rectangular wave signal VC having the same period as the triangular wave signal and one wire width apart from each other. An oscillation circuit 16 is provided that generates . The triangular wave signal VA and the first rectangular wave signal VB are supplied to an AND circuit 17. Also,
The upper triangular wave signal VΔ and the first rectangular wave signal VB are supplied to signal inversion circuits 1B and 19, respectively. Output signals VA and VB from the dirt floor signal inversion circuits 18 and 19 are supplied to an AND circuit 20. The output signal VD of the AND circuit 17 and the output signal VE of the AND circuit 20 are supplied to an OR circuit 21. The output signal VF of this OR circuit 21 is output as a triangular wave signal with a duty of -100%.

FIG. 8 is a diagram showing signal waveforms of each part of the principle circuit shown in FIG. 7. The signal inverting circuits 18 and 19 invert each of VA and VB, so the inverted signal VA.

As shown in FIG. 8, VB is shifted by half a cycle from each of VA and VB. On the other hand, since the AND circuit 17 outputs the signal VA only when the signal VB is at a high potential, only the waveform when the signal VA is rising is output as its output signal VD. Since the AND circuit 20 outputs the signal VA only when the signal VB is at a high potential, its output signal MVP
As such, only the waveform when the signal VA is rising is output.

Since the OR circuit 21 is supplied with the signals Vr) and VE, its output signal V' has a period twice that of the signals VA and VB and has a steep fall, as shown in the figure. The duty becomes a signal of 100%.

[Embodiment of the Invention] Next, an embodiment of the invention based on the above principle will be described with reference to FIG. In this embodiment circuit, the signal VA of the oscillation circuit 16 is supplied to the base of an NPN type transistor (hereinafter, all transistors whose type is not specified are assumed to be of the NPN type). The signal VB of the oscillation circuit 16 is supplied to the base of the transistor 32. The emitters of both transistors 31 and 32 are connected via emitter resistors 33 and 34, respectively, and both 1-transistors 31 and 32 constitute a differential pair 35. A constant current W is connected to the connection point of both emitter resistors 33 and 34 above.
One end of A36 is connected, and this constant DC current of 8!36 is supplied to the differential pair 35 as an operating current.

"-Note] ~ The emitters of transistors 37 and 38 are connected to the collector of transistor 31, and these transistors 37 and 38 constitute a differential pair 39. Further, a transistor 40 is connected to the collector of the transistors 1 to 32.
．． 410 emitters are connected, and the transistors 40 and 41 form a differential pair 42. The collectors of the transistors 31 and 40 are connected, and a load resistor 43 is inserted between the collector connection point and the power supply potential Vco. The collectors of the transistors 38 and 41 are connected, and a load resistor 44 is inserted between the collector connection point and the power supply potential Voc.

A pair of resistors 51.52 are inserted in series between the power supply potential Voo and the ground potential Vss, and the base of the transistor 53 is connected to the series connection point of the pair of resistors 51.52. The collector of this transistor is it
It is connected to the s potential Voc, and an emitter resistor 54 is inserted between the emitter and the ground potential Vss.

In other words, the circuit consisting of the resistors 51, 52, 54 and the transistor 53 receives the voltage divided by the resistors 51, 52 through the emitter follower circuit consisting of the transistor 53 and the resistor 54, and generates a constant low impedance voltage. It is designed to output a DC bias voltage.

And the DC bias voltage output from here is resistor 55
This DC bias voltage is supplied in parallel to the bases of the transistors 37 and 41 via the resistor 5.
6 in parallel to the bases of the transistors 38, 40. Further, the output signal VC of the oscillation circuit 16 is supplied in parallel to the bases of the transistors 37 and 41 via a resistor 57.

That is, a signal VC superimposed on a constant DC bias voltage is supplied to the bases of the transistors 37 and 41.

In this embodiment circuit, AND circuits 17, 20, . Signal inversion circuit 18, 19 and OR circuit 21
is composed of transistors and resistors other than the oscillation circuit 16, and the output terminal 58 corresponding to the output -10=10,000 terminal of the OR circuit 21 is connected to the transistor 38.4.
1 common collector.

Next, the operation of the circuit configured as above will be explained.

Now, in FIG. 8, the signal VA is at a low potential, and the signal V
When B is at a high potential, in the differential pair 35, the transistor 31 is turned off and the transistor 32 is turned on.

Therefore, the current of constant current 11i36 is l-
It flows only to the run raster 32 side. At this time, oscillation circuit 1
The output signal VC of No. 6 is at a high potential, and only the transistor 37 of the differential pair 37 and only the transistor 41 of the differential pair 42 are turned on. For this reason, through the transistors 41 and 32 in the on state, respectively,
A current from a constant current source 36 flows through the load resistor 44 . Therefore, the potential of the output terminal 58 is at a low potential. As the potential of the signal VA gradually increases from this state, the transistor 31, which has been in the off state until now, receives the signal VA.
A collector current flows as the potential rises. The current flowing through this transistor 31 flows through the transistor 37 which is turned on within the differential pair 37. Therefore, as the potential of the signal VA increases, the current flowing through the 1-herald transistor 41 gradually decreases. Therefore, output terminal 5
The potential of 8 gradually increases in the same way as the signal VF.

When the potential of the signal VA reaches VB, the signal VB is inverted to a low potential as described above. As a result, in the differential pair 35, the transistor 32 is turned off and the transistor 31 is turned on. The current of the constant current source 36 then flows only to the side of the transistor 31 that is in the on state. At this time,
The output signal VC of the oscillation circuit 16 is inverted to a low potential like the signal VB, and only the I transistor 38 of the differential pair 37 and only the transistor 40 of the differential pair 42 are turned on.

For this reason, transistors 38 and 31 are in the on state, respectively.
A constant current 11i36 flows through the load resistor 44 through the resistor 44 in series. Therefore, the potential of the output terminal 58 rapidly decreases to a low potential. When the potential of the signal VA gradually decreases from this state, a collector current begins to flow through the transistor 32, which has been in an off state, as the potential of the signal VA decreases. The current flowing through this transistor 32 is the same as the current flowing through the transistor 4 which is turned on within the differential pair 42.
0 and does not contribute to the output signal. Therefore, the signal V
As the potential of A decreases, the current flowing through the transistor 38 gradually decreases, and the potential of the output terminal 58 gradually increases like the signal VF. Thereafter, by operating in the same manner, a triangular wave signal having a period twice that of the signal VA is obtained at the output terminal 58. Then, by the signal VC, transistor 3
8 and 41 are instantaneously switched, and the current flowing through the load resistor 44 is instantaneously reduced to 0, resulting in a steep fall of the output signal, and as a result, the duty of the output triangular wave signal is approximately 100%. be done.

FIG. 2 is a circuit diagram showing the configuration of an applied example of the present invention.

This application example circuit includes two oscillation circuits 16A and 16B in which the value of the capacitor 14 and the value of the resistor 15 are set so that the periods of the signal VC are different, and the output signal of the oscillation circuit 16A with the longer oscillation period is A so-called tone ringer circuit is constructed by generating a triangular wave signal with a duty of approximately 100% as in the above embodiment, and amplitude modulating the output signal of the oscillation circuit 163 having a shorter oscillation period with this triangular wave signal. This is what I did.

In this application example circuit, the transistors 37 and 40
The current flowing through is input to a current mirror circuit 63 consisting of PNP type transistors 61 and 62. On the other hand, the current flowing through the transistors 38 and 41 is passed through another current mirror circuit 66 consisting of PNP type transistors 64 and 65.
is input. The output current of one of the current mirror circuits 63 is input to a current mirror circuit 69 consisting of NPN type transistors 67 and 68. The collector of a transistor 65 which serves as a current output terminal of the current mirror circuit 66 and the collector of a transistor 68 which serves as a current output terminal of the current mirror circuit 69 are connected, and the base of an NPN transistor 10 is connected to this collector common connection point. be done. The base of this transistor 70 is short-circuited to the collector, and a resistor 71 is connected between the collector and the power supply potential Vcc.
However, a resistor 72 is inserted between the emitter and the ground potential Vss. The base of the transistor 70 is connected to the base of an NPN transistor 73, and the emitter of this transistor 73 and the ground potential V
A resistor 74 is inserted between it and sB. As a result, a current as indicated by I in the waveform diagram of FIG. 3 flows through the collector of the transistor 73.

Further, in the oscillation circuit 163, the output signal VC1 of the oscillation circuit 16A is supplied via the resistor 15 to the connection point between the pair of resistors 11 and 12. Therefore, as shown in FIG. 3, the output signal VC2 of the oscillation circuit 16B has a short period during the period when the signal VC1 is at a high potential, and the period when the signal VC1 is at a low potential. becomes longer.

Further, the base of an NPN transistor 77 is connected to the output terminal of the oscillation circuit 16B via a resistor 76.
The collector of this transistor 77 is connected to the power supply Vcc, and the emitter is connected to the ground potential Vss via a resistor 78. Further, the base of this transistor 77 is connected to the collector of the transistor 73 via a resistor 79. Therefore, the output signal VC2 of the oscillation circuit 16B is modulated by the collector current I of the transistor 73, and the amplitude sequentially increases in a triangular waveform from the emitters of the transistors 1 to 7 as shown by Vout in FIG.
A signal whose frequency alternately changes every cycle is output.

It goes without saying that the present invention is not limited to the above-mentioned embodiments and can be modified in many ways. For example, in the embodiment circuit shown in FIG. 1, the case has been described in which the output terminal 58 is taken out from the common collector of the transistors 38 and 41, but it may be taken out from the common collector of the transistors 37 and 40.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a triangular wave generation circuit that can generate a triangular wave signal with a duty of 100%.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram of an applied example circuit of this invention, FIG. 3 is a waveform diagram of the applied example circuit, and FIG. 4 is a circuit diagram of a conventional circuit. FIG. 5 is a waveform diagram of the conventional circuit, FIG. 6 is a waveform diagram showing the triangular wave signal to be obtained by the present invention, FIG. 7 is a circuit diagram of the principle circuit of the present invention, and FIG. 8 is a diagram of the principle circuit of the above. FIG. 16...Oscillation circuit, 31.32.37.38.40.
41...NPN transistor, 35.39. '42
...Differential pair, 43°44...9 load resistance. Applicant's agent Patent attorney Takehiko Suzue Figure 1 - Only 〇 Figure 4 Figure 5 6 M Figure 7 Figure 8

Claims (1)

[Scope of Claims] An oscillation circuit that generates a triangular wave signal having a predetermined cycle and duty, and first and second rectangular wave signals that have the same cycle as the triangular wave signal and have different amplitudes, the emitters of which are coupled to each other, The first and second bases are supplied with the first rectangular wave signal and the triangular wave signal, respectively.
a first differential pair consisting of transistors; current source means for supplying a constant DC current to the first differential pair; each emitter being coupled to the collector of the first transistor, the base having a predetermined DC bias; a second transistor comprising third and fourth transistors to which the second rectangular wave signal superimposed on the voltage and a predetermined DC bias voltage are respectively supplied;
a fifth transistor whose emitter is coupled to the collector of the second transistor, whose collector is connected to the collector of the third transistor, and whose base is supplied with the predetermined DC bias voltage, and a collector; is connected to the collector of the fourth transistor, and has a base supplied with the second rectangular wave signal superimposed on the predetermined DC bias voltage; 1. A triangular wave generation circuit comprising: load means having one end connected to a collector connection point of the third and fifth transistors or a collector connection point of the fourth and sixth transistors.