JPS62108526A - Working method for semiconductor plate - Google Patents

Abstract

PURPOSE:To readily obtain constant and uniform thickness by connecting one conductivity type layer with one electrode, and applying a voltage positively biasing the other conductivity type layer to the layer. CONSTITUTION:Since an N-type layer is positive to a P-type layer when a voltage is applied in a range that a P-N junction does not break down between the N-type layer and the P-type layer of a silicon plate 3, accelerated ions flow from the N-type layer side to the P-type layer side, ion impact increases at the P-type layer side as compared with the N-type Layer side, and the etching velocity at the N-type layer becomes extremely small. Accordingly, if the thickness of the N-type layer is set to the thickness of a thin portion 23, a recess 24 which allows the thickness of the N-type layer to remain is formed. The impurity density, thickness of the P-type layer and the N-type layer are considered to form a P-N junction of the plate 3 so as not break down to a bias voltage necessary for the P-N junction. If a thin layer is necessary to be of P-type, a bias is forwardly applied to the P-N junction. Thus, a constant and uniform thin layer can be obtained.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention relates to a method for processing a semiconductor board, in which a thin part made of a layer of one conductivity type is formed in a predetermined region of a semiconductor board, such as a diaphragm for a semiconductor pressure sensor, by dry etching.

[Prior art and its problems]

The current mainstream dry etching method is the reactive ion etching (RIE) method, in which ions bombard the sample surface in plasma generated at a gas pressure of about 101 to 10-' Torr using a parallel plate plasma device. Etching is performed by accelerating the reaction. At this time, the active species adsorbed on the wafer surface and the substrate are excited to promote the etching reaction, or the wafer is bombarded with ions to create a damaged layer on the surface of the silicon, etc., and the cut silicon reacts with the active species. Various reaction promotion models have been considered to promote the reaction. FIG. 2 shows a typical RTEW arrangement, in which high frequency power is applied by a high frequency power source 5 between a grounded anode section 1 and a cathode section 2 supporting a sample 3. Anode part 1
and the cathode part 2 are insulated by an insulator 4, and the high frequency Wa
A profking capacitor 6 is connected in series to S to prevent direct current from flowing. The anode section 1, which also serves as a reaction tank, is provided with an inlet 7 and an outlet 8 for a halide gas as a reaction gas, and the cathode section 2 is provided with a cooling water inlet/outlet 9 for cooling the sample 3. In such a device, when high-frequency power is applied, a plasma 1 (l) is generated between the two electrodes 1 and 2, but the potential distribution between the two electrodes at that time is shown in Fig. 3. Since the area is smaller than that of the cathode section 1, which is the ground electrode, a negative DC voltage VdC is generated at the cathode.This VDC accelerates reactive ions and promotes the etching reaction. Although the reaction process is complicated,
Halides are formed on the surface of silicon etc. by chemical adsorption of fluorine and chlorine atoms. For example, a reaction occurs naturally between F atoms and silicon, and eventually Si
It becomes F* and is removed from the surface. When ion bombardment is added to this, the reaction at the bombardment surface is promoted. However, as shown in FIG. 4, when a mask 22 is covered with aluminum on the surface of a silicon plate 21 and a recess 24 is formed by plasma etching in which a thin portion 23 remains as shown by diagonal lines, Deep etching is required, and the greater the amount of etching, the more difficult it is to obtain a uniform thin layer 23 of constant thickness. Using the R[E device shown in Figure 2,
When etching is performed using a gas such as SF4 or NPz, the thickness of the layer 25 tends to be thicker at the periphery than at the center 23 of the recess 24, as shown by the dotted line 25 in FIG. It is in. Furthermore, when forming a large number of recesses on one silicon substrate, the thickness of each recess varies greatly over the entire surface of the substrate. The thickness after is 30±10
nA, which causes a decrease in yield and becomes a big problem.

[Purpose of the invention] The present invention solves the above-mentioned problems and makes it possible to easily obtain a layer with a constant and uniform thickness when dry etching a predetermined area of a semiconductor board from the surface to form a thin part with a constant thickness. An object of the present invention is to provide a method for processing a semiconductor board. [Key points of the invention]

The present invention applies high-frequency power between opposing electrodes with different areas, generates plasma in a reaction gas, and generates plasma from a predetermined area on one side of a semiconductor board disposed near one electrode with a small area. When dry etching to depth,
A PN junction parallel to the board surface is formed in advance on the semiconductor board, consisting of a layer of one conductivity type at the depth to be etched on one side and a layer of the other four shapes on the other side, and the layer of one conductivity type is By connecting to one of the electrodes and applying a voltage that positively biases the layer of the other conductivity type with respect to that layer, the ion bombardment on the part of the semiconductor plate that is not to be etched is weakened, and many ions are transferred to the part to be etched. The above object is achieved by applying an impact so that a layer of one conductivity type remains and a layer of uniform thickness is obtained.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. A silicon plate 3 supported by a cathode part 2 and to which high-frequency power is applied by a high-frequency power supply 5 between the anode part 1 and the grounded anode part 1 is insulated by an insulator 11 . A PN junction is formed in the silicon plate 3, which is placed on the insulator 11 with the P layer on top having a thickness equal to the depth to be etched. Silicon plate 3-2
The M side has a metal layer 22 attached to the surface. It is connected to the cathode 2 via a conducting wire 13, and the N-layer side 12 is connected to an insulator 11. to apply a positive DC voltage to this cathode.
It is connected to a DC power source 15 by a conductor 14 passing through 12. In addition to the capacitor 6, the high frequency power supply circuit naturally includes an impedance matching circuit (not shown). The metal layer 22 is a protective mask against etching and the reactive gas is SF4. In the case of NF3 or the like, it is possible to use a material made of NF3 or the like, or one made of Au or the like. Using such a device, a reaction gas is introduced from the introduction lower, and the temperature is adjusted to about 0.5 Torr and the power source 5 is used to control the reaction gas to 100
~200W of high frequency power is applied to the anode 1. When applied between the cathodes 2, plasma 10 is generated and etched at a speed of several 87 minutes. In this case, according to the present invention, by applying a voltage between the N layer and the P layer of the silicon plate 3 using the power supply 15 within a range that does not cause breakdown of the PN junction, the N layer becomes a positive potential with respect to the P layer. Therefore, the accelerated ions become NW4
The etching starts to flow from the surface side to the pH side, and the ion bombardment is greater on the PR side than on the N layer, and the etching rate in N1N becomes extremely low. Therefore, if the thickness of the N layer is set in advance to the thickness of the thin portion 23 to be formed as shown in FIG. 4, the recess 24 with the thickness of the N layer remaining will be formed. The formation of the PN junction on the silicon plate 3 involves the use of P stones,
It is important to consider the impurity concentration, thickness, etc. of the N layer. It is also important to pay attention to the cleanliness of the PN junction surface so that leakage current does not increase during PN junction biasing. The present invention can be applied similarly even when the cathode portion is grounded. Also, if the thin layer you want to form needs to be P-type, apply a voltage that makes the pH positive with respect to the N layer, that is, forward bias the PN junction. Therefore, the bias is limited to a low voltage, but devices such as reactive ion beams using electron cyclotron resonance plasma etc. have been effective with low bias voltages.

【Effect of the invention】

According to the present invention, when a predetermined region of a semiconductor board is etched into a concave shape using a dry etching method, a target residual thickness of the concave portion is formed in advance as a layer of a different conductivity type, and this PN junction is By applying a positive voltage to that layer, the etching depth can be automatically and precisely controlled to reach that layer, making it possible to obtain a constant and uniform thin layer. Therefore, it can be applied very effectively especially when forming a large number of diaphragm parts of a predetermined thickness in order to obtain a large number of semiconductor pressure sensor chips from one semiconductor substrate.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a reactive ion etching apparatus according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional reactive ion etching apparatus, and FIG. 3 is an anode in the apparatus of FIG. The potential distribution diagram between the cathode parts, and FIG. 4 is a cross-sectional view showing a silicon plate in an etched state. l: anode, 2: cathode, 3: silicon plate, 5: high frequency power supply, 7: gas inlet, 8: gas outlet, 10: plasma,
ICl3: insulator, 24: recess. Figure 1

Claims (1)

[Claims] 1) High-frequency power is applied between opposing electrodes with different areas to generate plasma in the reaction gas and dry it to a predetermined depth from a predetermined area on one surface of a semiconductor board placed near one electrode with a small area. When etching, a PN junction parallel to the board surface is formed in advance on the semiconductor board, consisting of a layer of one conductivity type at the depth to be etched on one side and a layer of the other conductivity type on the other side, and A method for processing a semiconductor board, comprising: connecting a layer of one conductivity type to the one electrode, and applying a voltage that positively biases a layer of another conductivity type with respect to the layer.