JPS62106666A - Insulated gate transistor - Google Patents

Abstract

PURPOSE:To enlarge the allowance of an alignment accuracy and reduce the labor for mask alignment by a method wherein a source line and a drain line are so provided as to cross over a gate line with an insulating layer and a semiconductor layer, whose widths are equal to or wider than the width of the gate line, in between. CONSTITUTION:An insulating layer 6 and a semiconductor layer 5 are formed on a gate line 2. The widths of the insulating layer 6 and the semiconductor layer 5 are equal to or wider than the width of the gate line 2. A source line 3 and a drain line 4 are provided in parallel to each other on the semiconductor layer 5 in the direction of crossing over the gate line 2. With this constitution, the allowance of an alignment accuracy is enlarged so that the labor of mask alignment can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to insulated gate transistors, and particularly to gate I transistors.
- relates to an insulated gate transistor in which a source line is formed across the line.

[Prior Art] Below, as an example of a conventional insulated gate transistor,
A thin IV2 transistor (hereinafter referred to as TPT) array used in liquid crystal display devices and the like will be described with reference to FIG.

Fig. 3 is a diagram showing one configuration of a conventional TFT array "J3 element," Fig. 3 (2L) is a partial top view, and Fig. 3 (b) is an AA
FIG.

In FIG. 3, reference numeral 1 denotes a substrate made of glass or plastic, on which a pixel electrode 7 and a gate line 2 are formed. A bulge 2' is formed on this gate line 2, and the end thereof becomes a gate electrode. An insulating layer 6 and a semiconductor layer 5 are formed on the bulge 2'l-, and a source electrode and a drain electrode, which are the ends of the bulge 3' of the source line 3, are formed facing each other thereon. There is. This drain electrode is the end of the drain line 4 connected to the pixel'-hypode 7.

The gate line 2 is provided in one direction in the gap between each pixel electrode formed in a matrix, and the source line 3 is connected to the gate line 2.
provided in the other direction across the The source line 3 is formed via an insulating layer 6 and a semiconductor layer 5 as shown.

[Problems that 95 Ming attempts to solve] - The TFT array with the above structure is manufactured using photolithography, but because of its complicated shape, strict alignment viscosity is required, making mask alignment very time-consuming. There was a problem. In addition, the shape of the TPT channel is determined by the arrangement of the source and drain electrodes, but when applying resist and forming the source and drain electrodes using a normal photolithography process, the corners of the electrodes tend to become rounded. It has been very difficult to form channels of the correct size and shape to market.

In view of the problems of the conventional method, the present invention increases the allowable range of alignment viscosity, reduces the distance P required for mask alignment, and ensures stable insulated gate transistors with a channel shape as designed. It is intended to provide the following information.

[Means for solving problems] In other words, the problem in item L is related to the gate line.

A non-occurring IJI characterized in that a source line and a drain line are provided that cross the gate line via an insulating layer and a semiconductor layer whose width is the same as or exceeds the width of the gate line.
solved by an insulated gate cedar transistor.

[Function] The insulated gate transistor/transistor of the present invention has an insulating gate transistor with a width equal to or greater than the width of the gate line. The channel width is determined by the width of the gate line, a source line and a drain line are provided across the gate line, and a pressure path is established between the source line and the drain line to form an insulated gate transistor. [Embodiment] Hereinafter, embodiments of the present invention will be explained with reference to the drawings. A TFT array used in liquid crystal display devices and the like as an insulated gate transistor of the present invention will be described.

FIG. 1 is a diagram showing one component of an embodiment of a TFT array of the present invention, FIG. 1(a) is a partial page view, and FIG. 1(b)
is a vertical cross-sectional view of the BB' portion.

As shown in FIG. 1, an insulating layer 6 and a semiconductor layer 5 are provided on the gate line 2L, and the widths of the insulating layer 6 and semiconductor layer 5 are equal to or wider than the width of the gate line 2. . On the semiconductor layer 5, source lines 3 and drain lines 4 are provided in rows in a direction crossing the gate line 2. That is, a part of the gate line 2 becomes the gate electrode, and a part of the source line 3. A part of the drain line 4 serves as a source electrode and a drain electrode. The length of the channel portion of the TPT having the above configuration is determined by the distance between the source &13 and the drain line 4, and the channel width is determined by the width of the gate a. In other words,
The channel width is constant and stable regardless of the arrangement of the source electrode and the drain electrode. Fig. 2 is a diagram showing one component of another embodiment of the TFT array of the present invention, and Fig. 2 (a)
is a partial cross-sectional view, and FIG. 2(b) is a longitudinal cross-sectional view of the CC' section.

Note that /:5 is not shown on the insulating layer 6 and the semiconductor in the partial plan view of (a).

In FIG. 2, the drain line 4 and the pixel electrode 7 are formed of the same transparent electrode, and the source line 3 is also formed of a transparent electrode. An old conductor layer 5 is placed on top of these transparent Ill'++2 poles. An insulating layer 6 is formed, and further a gate line 2 is formed. Even in the TFT array with this configuration,
The channel part is determined by the width of the gate line, and the channel part is constant and stable regardless of the arrangement of the ``--'' and the train'--center poles.

The insulated gate transistor of the present invention is suitably used in a device in which a source line is formed across a gate line, and insulated gate transistors are formed in a matrix, such as a TFT array used in a liquid crystal display device, etc. .

[Effects of the Invention] -1 Detailed Description II As described above, according to the insulated gate type transistor/distor according to the present invention, the tolerance range of alignment precision 1 is large, the mask alignment 1 is reduced, and Since the rounding of the corners due to etching does not affect the channel shape, an insulated game I-type transistor with a box shape according to fi is stable. [Approximately +7): A large reduction in AL and cost is possible.Insulated gate type transistor and 1.DELTA.' are included in the wiring section, so it is possible to improve the mounting efficiency.

[Brief explanation of drawings]

FIG. 1 is a diagram showing one component of an embodiment of the TFT array of the present invention, FIG. 1(a) is a partial plan view, and FIG. 1(b) is a partial plan view.
is a vertical cross-sectional view of the BB' portion. FIG. 2 does not show one component of another embodiment of the TFT array of the present invention [4, FIG. 2(a) is a cross-sectional view of the portion 1i, and FIG. Fig. 3 is a diagram showing a conventional rFT:?ray structure I & element, Fig. 3(a) is a partial plan view, and Fig. 3(b) is an AA'
FIG. 1...Substrate 2...Gate line 3I11-Source line 4-ΦDrain line 5...Semiconductor layer 6-Fist...1 Insulating layer 7... ...Electrode agent in picture 2 Patent attorney 111 Ding Mo @1 Figure 2 (G)

Claims (1)

[Claims] An insulated gate type characterized in that a source line and a drain line are provided across the gate line through an insulating layer and a semiconductor layer whose width is the same as or exceeds the width of the gate line. transistor.