JPS62102176U - - Google Patents
Info
- Publication number
- JPS62102176U JPS62102176U JP19541885U JP19541885U JPS62102176U JP S62102176 U JPS62102176 U JP S62102176U JP 19541885 U JP19541885 U JP 19541885U JP 19541885 U JP19541885 U JP 19541885U JP S62102176 U JPS62102176 U JP S62102176U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- withstand voltage
- control circuit
- measured
- multiple types
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Testing Of Individual Semiconductor Devices (AREA)
- Testing Relating To Insulation (AREA)
Description
第１図は本考案の耐圧測定回路の原理ブロツク
図、第２図は動作タイミング図、第３図は本考案
の耐圧測定回路の実施例を示す回路図、第４図は
従来方式の説明図である。
第１図、第３図において、１は定電圧回路、２
はスイツチ回路、３は制御回路、４は被測定トラ
ンジスタ、５は記憶回路、６は電流源である。
Fig. 1 is a principle block diagram of the withstand voltage measuring circuit of the present invention, Fig. 2 is an operation timing diagram, Fig. 3 is a circuit diagram showing an embodiment of the withstand voltage measuring circuit of the present invention, and Fig. 4 is an explanatory diagram of the conventional system. It is. In Figures 1 and 3, 1 is a constant voltage circuit, 2
3 is a switch circuit, 3 is a control circuit, 4 is a transistor to be measured, 5 is a memory circuit, and 6 is a current source.
Claims (1)
回路１と、 該定電圧回路１から発生する複数種類の電圧を
順次に切り替えるスイツチ回路２と、 該スイツチ回路２の切り替えを制御する制御回
路３と、 被測定物４の耐圧が測定されると該制御回路３
により記憶回路５に記憶し、該被測定物の耐圧電
圧値を把握することを特徴とした耐圧測定回路。[Claims for Utility Model Registration] A constant voltage circuit 1 that generates multiple types of voltages for measuring withstand voltage, a switch circuit 2 that sequentially switches between multiple types of voltages generated from the constant voltage circuit 1, and the switch circuit 2 a control circuit 3 that controls switching of the control circuit 3; and a control circuit 3 that controls the switching of
A withstand voltage measuring circuit is characterized in that the withstand voltage value of the object to be measured is memorized in the memory circuit 5 and the withstand voltage value of the object to be measured is grasped.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541885U JPS62102176U (en) | 1985-12-18 | 1985-12-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19541885U JPS62102176U (en) | 1985-12-18 | 1985-12-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62102176U true JPS62102176U (en) | 1987-06-29 |
Family
ID=31153291
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19541885U Pending JPS62102176U (en) | 1985-12-18 | 1985-12-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62102176U (en) |
-
1985
- 1985-12-18 JP JP19541885U patent/JPS62102176U/ja active Pending