JPS62100850A - Processing system for main memory access - Google Patents

Abstract

PURPOSE:To secure the advantages of a memory element having a fast access time by stoting previously a memory flag indicating an access mode into a memory constituting an address conversion mechanism. CONSTITUTION:A memory 2 is retrieved by 5-9 bits of a real address 1 to obtain a physical address that gives an access to a main memory. Then the segment number of an access subject is read out together with an upper address within the segment and a memory flag for selection of an access mode. The lower addresses within a segment formed by 10-25 bits of the address 1 are combined with the upper addresses within said segment for decision of the address within the segment. Then an access is given to the corresponding physical address. In this case, the specific access time is instructed by said memory flag read out of the memory 2.

Description

[Detailed Description of the Invention] [Summary] In a data processing device, a plurality of types of segments with different access modes are mixed in the main storage device, and a plurality of types of segments with different access modes are mixed in the main storage device, and in the memory that constitutes the real address/physical address translation mechanism. The access mode for each segment above is
It is disclosed that the information is stored as a flag, and segments with different access modes are accessed under each mode.

[Industrial application field]

The present invention relates to a main memory access processing method, particularly to a data processing apparatus having a main memory device in which memory segments with different access modes coexist.

The present invention relates to a main memory access processing method in which a memory flag indicating the above-mentioned access mode is provided in a memory constituting a real address/physical address conversion mechanism, and each segment can be accessed under each access mode.

[Conventional technology]

With the recent remarkable progress in semiconductor technology, the degree of integration and access time of memory elements that make up the main memory have improved, and the capacity of the main memory has increased and the access time has become faster. . For example, initially 64KRAM, 15
For example, a main memory device composed of 0 ns elements is reconfigured into a new main memory device composed of 256 KRAM, 120 ns elements.

On the user side, on the other hand, there is an increasing demand for an optimal storage system for each user, and we need to improve the processing capacity of the computer system that was originally introduced.

The above tα device is added.

Therefore, it has become common for main memory units to have different access modes, such as access times, as the main memory segments.

Conventionally, in the case of this type of mixed main memory.

The access time to the main storage device was adjusted to match the slower access time.

[Problem that the invention attempts to solve]

In the conventional case described above, the advantage of a memory element having a fast access time cannot be enjoyed.

[Means for solving the problem J] The present invention solves this problem, and allows access according to the access time of each of the three.

FIG. 1 shows a basic configuration diagram of the present invention.

In the figure, 1 represents a real address, and 2 represents a memory forming a floating electronic memory address mechanism (hereinafter referred to as FMA mechanism).

The main storage device whose illustration is omitted in FIG.

For example, it is composed of eight segments, and each segment is composed of four memory units.

Each memory unit consists of 4MB.

The same goes for the conventional case, but when a real address 1 is given, in order to determine which memory unit of which segment the address corresponds to, 2 is stored, for example, in the storage controller (MSC'). An MA mechanism is provided to index the memory 2 shown in FIG. In the conventional case, the memory flag (
MSU FLG) did not exist.

By #5 to #9 bits of real address 1.

Memory 2 is indexed. There are a total of 32 pieces in memory 2.
×8) memory units, (I
) validity indicator bits (valid bits or indicated as V, B); and (ii) segment number (SEG).
(NO,) and (iii) the upper address within the segment (S
EG) and (iv) memory flags prepared in the present invention (lisU FI) are described.
There is.

[Effect]

To obtain the physical address for accessing the main memory based on real address 1, as shown in FIG. 1, memory 2 is indexed by #5 bit (7#9 bit) of real address 1.

Segment number (SEG) of the object to be accessed
), the upper address within the segment (upper within SEG), and the memory flag for access mode selection (M
SU FLG) will be put on sale. Then, the intra-segment lower address based on the #10 bit to #25 bit of real address 1 and the above-mentioned intra-segment upper address are combined and determined as the intra-segment address. Note that #26 bisoto to #31 pino1 to real address 1 give addresses within the block.

That is, needless to say, the segment 1 to number determines which segment is to be accessed, and the intra-segment address determines the address within the segment (indicating which address on which memory unit). , the physical address is accessed.

At this time, in the case of the present invention, a memory flag (MSU FLG) is read from the memory 2, and its contents indicate at what access time the access should be made.

〔Example〕

FIG. 2 shows the configuration of an embodiment of the present invention. The reference numeral 2 in the figure corresponds to FIG. 1, and 10 is a central processing unit.

11 is a channel control device, 12 is a main storage device, 13 is a storage control device, 11.3-0 to 113-7 are memory segments l-, 14, 15, . . . , memory units, respectively. represents. Also, 16 is the segment
Number decoder 17 represents a segment selection section. 18-0 and 18-1 are counters each having two votes. As an access method for two types of segments with different access times, the initial value of the counter to be used is set differently depending on the access time.

It performs counter control. Furthermore 19-0 and 19-
1 represents an access address port, and two ports are provided separately corresponding to the above counters.

Corresponding to the given real address, memory 2 is indexed and based on its contents.

(i) Decide which segment to access.

(11) Determine the address within the segment.

(■) Determine access time.

The storage control device 13 accesses the main storage device 12.

In the case shown in FIG. 2, it can be seen from the contents of the memory 2 that segments with different access times are constructed as shown in FIG. That is, segment #0 has an access time corresponding to memory flag "0", +
component #1 has an access time corresponding to memory flag "1". Then, when memory units are accessed in sequence, memory units within the same segment are accessed in sequence.

In contrast to the above, the information in the memory 2 may be described as shown in the fourth section (T). In this case, as shown in FIG. 5, segment #0 has an access time corresponding to the memory flag "0", and segment #1 has an access time l corresponding to the memory flag "1". Also, when memory units are accessed sequentially,
Segment #0 and segment #1 are accessed alternately.

〔Effect of the invention〕

As explained above, according to the present invention, memory segments having different access modes such as access time can be accessed under each access mode. It becomes possible to enjoy it.

[Brief explanation of drawings]

FIG. 1 shows the principle configuration of the present invention, FIG. 2 shows the configuration of an embodiment of the present invention, and FIGS. 3 to 5 are explanatory diagrams illustrating examples of memory configurations. In the figure, 1 is a real address, 2 is a memory constituting an address conversion mechanism, ]o is a central processing unit, 11 is a channel control device, 12 is the above-mentioned Fi device, 13 is a storage control device, 113
-Q, 113-1.・Old... indicates a memory segment.

Claims (1)

[Scope of Claims] An access source device including a central processing unit (10) and a main storage device (12) consisting of a plurality of segments (113-i), and capable of responding to access requests from the access source device. In a data processing device that is provided with an address conversion mechanism that converts a memory access real address into a physical address including a segment number and an intra-segment address, in the main storage device (12),
Segments that can be accessed in different access modes (
113-i) so that they can be mixed, and a memory flag (MSUFLG ), and when accessing the main storage device (12) in response to an access request from the access source device, the address translation mechanism is accessed and based on the memory flag (MSUFLG). , a main memory access processing method characterized in that an access mode is set.