JPS6199993A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To transmit a write signal and a read-out signal without causing a level loss, to realize low power consumption, and to execute an operation at a high speed by using a CMOS clocked inverter circuit as an input circuit and an output circuit. CONSTITUTION:At the time of a write operation, a write control signal WE becomes a high level, WE becomes a low level, an input use CMOS clocked inverter circuit IV1 becomes an operating state, and a write signal supplied from an input terminal IN is inputted. In a CMOS inverter circuit IV2, a DC current is consumed only when an input signal is varied, therefore, the DC current can be reduced remarkably. When the write control signal WE becomes a low level, and WE becomes a high level, IV1 becomes a non-operating state, a feedback use CMOS clocked inverter circuit IV3 is switched to an operating state, and by a positive feedback loop by IV2 and IV3, the inputted write signal is held. When a control signal OE becomes a high level, a CMOS clocked inverter circuit IV4 becomes an operating state, and storage information of a holding state is sent out to an output terminal OUT.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a semiconductor integrated circuit device, and for example, a semiconductor integrated circuit device including a RAM (random access memory).
The present invention relates to a technology effective for use in MOS (complementary MO3) gate arrays.

[Background technology]

A circuit as shown in FIG. 3 is known as a memory cell constituting a RAM built into a CMOS gate array (see Nikkei Electronics J, page 120, Nikkei McGraw-Hill, February 28, 1983).

This memory cell includes two CMOS clocked inverter circuits I whose inputs and outputs are cross-wired.
V5. A flip-flop circuit composed of I V 6 and an N-channel type transmission gate (MO5FETQ20. Q21. In this memory cell, for example,
When a high-level write signal from data 1 is supplied to the input of the CMOS clocked inverter circuit via the transmission gate MO3FETQ20, a level loss of the write signal occurs by the threshold voltage of the MO3FETQ20.

For this reason, the P-channel MOS FET constituting the CMOS clocked inverter circuit IV5 is not completely turned off, so there is a problem that DC current is consumed in the CMOS clocked inverter circuit IV5 during this time. . The above level loss similarly occurs when high level storage information is read out as data 1 or data 2 from the memory cell. Therefore, the 0M03 circuit (not shown) that receives the data 1 or data 1 signal also consumes direct current. Therefore, the current consumption of the memory cell increases and its operating speed decreases.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a CMOSRAM that achieves low power consumption and high-speed operation.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief summary of typical inventions disclosed in this application is as follows.

That is, a pair of CMOS clocked inverter circuits that transmit write signals and read signals respectively by control signals, a CMOS inverter circuit that receives the output of the human-powered CMOS clocked inverter circuit, and this CMOS
Memo 1. The inverter circuit and the input/output are cross-connected, and the CMOS clocked inverter circuit for input and the CMOS clocked inverter circuit are operated in a complementary manner. This is what constitutes recell.

〔Example〕

FIG. 1 shows a logic circuit diagram of an embodiment of a memory cell according to the present invention.

Input terminal IN is coupled to the input of a CMOS clocked inverter circuit IVI that is activated by write control signal WE. The output of this CMOS clocked inverter circuit IVI is coupled to the input of a CMOS inverter circuit IV2. This CMOS inverter circuit IV2
The output of is coupled to the input of a CMOS clocked inverter circuit IV3 which is activated by an inverted signal WE of the write control signal WE. The output of this CMOS clocked inverter circuit IV3 is fed back to the input of the CMOS inverter circuit IV2. In other words,
The CMOS inverter circuit IV2 and the CMOS clocked inverter circuit IV3 constitute a launch circuit by having their inputs and outputs cross-connected to each other.

The output of the CMOS clocked inverter circuit IV3 is a CM which is activated by the read control signal OE.
The signal is sent to the output terminal OUT via the OS clocked inverter circuit ``4''.

Note that the above CMOS clocked inverter circuit IVI,
Control signals W supplied to IV3 and IV4, respectively;
Signals WE and OE are typically supplied to the N-channel O3FET, and as will be described later, their inverted signals are supplied to the P-channel MO3FET.

The operation of the above memory cell will now be described.

During a write operation, a non-inverted write control signal W is used to control the operation of the CMOS clocked inverter circuit IVI.
When E is at high level, the feedback CM that forms the latch circuit
The inverted write control signal WE that controls the OS clocked inverter circuit IV3 is set to low level. This allows the input CMOS clocked inverter IV1
is activated and takes in the write signal supplied from the input terminal IN. At this time, the above return commercial
The OS inverter circuit IV3 is rendered inactive and its output is placed in a high impedance state. Therefore, the output of CMOS clocked inverter circuit IVI and the output of CMOS inverter circuit TV2 are determined according to the write signal.

In such a write operation, the input CMOS clocked inverter circuit IVI transfers a high level such as the power supply voltage Vcc according to the write signal or a low level such as the circuit ground potential to the CMOS inverter circuit IV2 without level loss. feed the input. This allows CMO
Since the S inverter circuit IV2 consumes DC current only when the signal changes, the DC current during the write operation period can be significantly reduced.

When the non-inverted write control signal WE is set to low level and the inverted write control signal WE is set to high level, the input CMOS clocked inverter circuit IVI becomes inactive, and the feedback CMOS clocked inverter circuit IV
3 is switched to the active state. As a result, the output of the CMOS clocked inverter circuit IVI for input is placed in a high impedance state (non-operating state), and a positive feedback loop formed by the CMOS inverter circuit IV2 and the CMOS clocked inverter circuit IV3 allows the above-mentioned write signal to be input. Hold.

Next, when the readout (output) control signal OE is set to high level, the CMOS clocked inverter circuit IV4 is activated, and the stored information in the held state is transferred to the output terminal OU.
Send it to T. At this time, the output level of the output CMOS clocked inverter circuit IV4 is set to a high level such as the power supply voltage Vcc according to the stored information or a low level such as the ground potential of the circuit.

Note that the memory cells described above are arranged in a matrix, thereby forming, for example, a RAM with a relatively small storage capacity built into a CMOS gate array. Therefore, the control signals WE, OB, etc. are generated only for memory cells selected by an address decoder (not shown).

FIG. 2 shows a circuit diagram of a specific embodiment of the memory cell. Each circuit element in the figure is a well-known 0MO3
(Complementary type MO3)! Manufacture of 4-product circuit.

technology is formed on a semiconductor substrate, such as a piece of single crystal silicon. In the figure, the MOSFET with a straight line added between the source and drain is a P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. N channel MOS
The FET has a source region, a drain region formed on the surface of the semiconductor substrate, and a gate made of polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region with a thin gate insulating film interposed therebetween. Consists of electrodes. The P-channel MOS FET is formed in an N-type well region formed on the surface of the semiconductor substrate.

Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of N-channel MOS FETs formed thereon. The N-type well region constitutes the base gate of the P-channel MOS FET formed thereon.

CMOSMOS that receives write signal from input terminal IN
Clocked inverter V1 connects the circuit's ground potential point and rI
i N-channel MO3FET Q5 . Q6 and P channel MO3FETQ
? , QB. Above N channel MO3
FETQ5 and P channel MOS FETQB
The gates of are shared and coupled to the input terminal IN. Further, a non-inverted write control signal WE is supplied to the gate of the N-channel MOSFET Q6, and an inverted write signal WE is supplied to the gate of the P-channel MOSFET Q7. The connection point between the 19-channel MO5FETQ6 and the P-channel MO5FETQ7 is used as an output.

The CM OS clocked inverter circuit IVI receives the output of the 0MO5-(inverter circuit IV2S, and the N-channel MOS FETQi 3 and P
It is composed of a channel MOSFETQ14. These MOSFETQI 3. The gate of Ql 4 is shared and coupled to the output of the upper E CFJ OS clocked inverter circuit IVI. In addition, the above MOSFET
Q13. The connection point of Q14 is the output, and the P-channel MO3FET Q12 and the N-channel M constitute a CMOS clocked inverter circuit IV3, which is constructed from a circuit similar to the CMOS clocked inverter circuit ■Vl described above.
Coupled to the gate of OSFETQ9. In order to operate this CMOS clocked inverter circuit IV3 in a complementary manner to the CMOS clocked inverter circuit IVI, contrary to the CMOS clocked inverter circuit IVI, the gate of the N-channel MO3FET QIO is
An inverted write control signal WE is supplied, and the P channel M
A non-inverted write control signal WE is supplied to the gate of O3FETQIl. Above N-channel MO3FETQ
The connection point between IO and P-channel MO3FETQI 1 is the output, and the above CMOS clocked inverter circuit I
It is commonly connected to the output of VI, the input of the CMOS inverter circuit IV2, and the input of an output CMOS clocked inverter circuit IV4, which will be described next.

The CMOS clocked inverter circuit IV4 is connected to the CM
It is constituted by a circuit similar to the OSMOS clocked inverter VI, and the gates of the N-channel MO5FETQI and the P-channel MO3FETQ4 are the commonly connected input terminals.

In addition, a non-inverted read signal OE is supplied to the gate of the N-channel MOSFET Q2, and a non-inverted read signal OE is supplied to the gate of the N-channel MOSFET Q2.
An inverted read signal OR is supplied to the gate of FETQ3. The connection point between the MO5FETs Q2 and Q3 is made into an output and coupled to the output terminal OUT.

The arrangement of each MOS FET in this embodiment is drawn in the same arrangement as the layout actually formed on the semiconductor substrate. The memory cell of this embodiment has 14 elements, which is larger than the memory cell of FIG. 3 (10 elements). However, C.M.O.
SMOS clocked inverters VI, rV3 and IV4
A series type P-channel MO5FET Q3.
Q4 etc. and N++'/nel MO5FETQ1. Q2, etc. can be connected in series using a common source and drain region, and are P-channel MO5FETs Q4, . Q
8. Q12 and Q14 and N-channel MOSFET Q1
．． Q5. The sources of Q9 and Q13 can be formed by a common semiconductor region. As a result, the layout area for forming the memory cell of this embodiment can be made as small as that of the circuit shown in FIG. 3 above.

〔effect〕

(1) By using CMOS clocked inverter circuits as input and output circuits, write signals and read signals can be transmitted without level loss. This provides the effect of preventing the generation of DC current that constantly flows in the CMOS inverter circuit constituting the launch circuit that receives the write signal and the 0M05 circuit that receives the read signal.

(2) According to (1) above, since it is possible to take in the VB signal and send out the read signal without any level loss, it is possible to achieve the effect of speeding up the operation.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say, for example, the 0M03 circuit includes a P-channel MOS F on an N-type semiconductor substrate.
ET is formed and an N-channel MO is formed on the P-type well region.
A 3FET may be formed, and the power supply voltage may be a negative voltage.

[Application field]

The present invention can be widely used in semiconductor integrated circuit devices including a RAM, such as a CMOS gate array.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of a memory cell according to the present invention, FIG. 2 is a circuit diagram showing an embodiment of the specific circuit, and FIG. 3 is an example of a conventional memory cell. FIG. IVI, IV3. IV4...0MO5 R07 inverter circuit, IV2...CMOS in-tweeter circuit Fig. 1 JE Fig. 2 Fig. 3

Claims (1)

[Claims] 1. A first CMOS clocked inverter circuit that receives a write signal and is activated by a write control signal, a CMOS inverter circuit that receives an output of this CMOS clocked inverter circuit, and this CMOS inverter circuit. a second CMOS clocked inverter circuit that receives an output signal of the circuit, is activated by the write signal in a complementary manner to the first CMOS clocked inverter circuit, and returns its output to the input of the CMOS inverter circuit; and a third CMOS clocked inverter circuit which receives the output signal of the second CMOS clocked inverter circuit and is activated by a read control signal, and includes a RAM in which memory cells are arranged in a matrix. Semiconductor integrated circuit device. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is constituted by a CMOS gate array.