JPS6198020A - Ed type directly coupled mesfet logic circuit - Google Patents

Abstract

PURPOSE:To prevent a failure in operation even when the threshold value of the E-FET of a switch element is almost zero by giving a transfer gate a sufficiently high threshold value in a directly coupled field-effect transistor circuit (DCFL). CONSTITUTION:A logical gate part E-FET5 has its threshold value nearly 0V and also has slight variance and is sometimes at a negative side as to DCFL composed of an N-channel GaAs MESFET. The FET3 constituting the transfer gate, however, has a sufficiently high threshold value, so it never turns on almost at 0V, so that there is no failure in operation when the transfer gate is off. A D-FET4 as a load is a normally on type, so there is not such malfunction that it turns off. Therefore, the variance when the threshold value of the E-FET of the switch element is set almost to 0V is irrelevant to the operation and a high-speed GaAs integrated circuit is manufacture with high yield.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an ED type direct-coupled MESFET logic circuit used in a compound semiconductor integrated circuit such as GaAs capable of ultra-high-speed operation. , which allows you to quickly and easily create high-density compound semiconductor integrated circuits.
This relates to a D-type directly connected MESFET logic circuit.

Conventional GaAs integrated circuits can operate at higher speeds than Si integrated circuits because the electron mobility of GaAs is several times higher than that of Si and because a semi-insulating substrate can be used.

Therefore, in recent years, small-scale GaA on the SSISMSI scale has been developed.
s integrated circuits are beginning to be put into practical use.

However, the commercialization of highly integrated GaAs integrated circuits has been delayed due to the low yield.

FIG. 1 shows an example of an I) CFL circuit (direct-coupled field effect transistor logic circuit), which is the most promising circuit for such a highly integrated GaAs integrated circuit.

In the illustrated DCFL circuit, a basic gate circuit is constituted by a depletion type field effect transistor (hereinafter referred to as FET) 1 which constitutes a load resistance and an enhancement type FET 2 which constitutes a switch element. .

FETI has its drain connected to the power supply, its source connected to the drain of FET2, and its gate connected to the source to make the depletion type FETI conductive.

On the other hand, the gate of the second enhancement type FET serves as an input, its drain serves as an output, and its source is grounded.

The drain, that is, the output of the enhancement type FET2 is connected to the drains of the enhancement type F and ET3 that constitute the transfer gate. A transfer control signal such as a clock pulse is applied to the gate of the enhancement type FET 3, and its source is connected to the next basic gate circuit consisting of FETs 4 and 5 configured in the same manner as FETI and 2. connected to human power.

Thus, by combining basic gate circuits and transfer gates, a multistage logic gate can be constructed, and the above-mentioned DCFL circuit becomes one of the basic circuits that constitute an integrated circuit.

DCFL circuits with ED configuration have advantages such as simple circuits because they can be directly connected.Furthermore, compared to DCFL circuits with so-called EE configuration, they are superior in switching speed and power consumption, and are highly integrated. suitable for

Problems that 3'1J13 attempts to solveHowever,
Normally, the gate electrode of FET used in GaAs integrated circuits is realized by Schottky contact, so DCFL
In the circuit, the high level voltage that can be applied to the gate electrode is
It is clamped to a low voltage (#0.7V) below the Schottky potential barrier, so the logic amplitude is small. For this reason,
In a DCFL circuit using GaA, sMESFET,
Precise control of the MESFET threshold voltage (gate voltage at which drain current stops flowing) is required. In particular, if the threshold voltage of the enhancement type FET is set near zero volts where high-speed operation can be expected, the operating margin of the GaAs integrated circuit against variations in the threshold voltage becomes extremely small for reasons explained later.
The yield of aAs integrated circuit chips suddenly drops. This was the most important problem when putting GaAs integrated circuits into practical use.

This problem is not limited to GaAs semiconductor integrated circuits but is common to compound semiconductor integrated circuits.

Therefore, the present invention utilizes the conventional compound semiconductor MES described above.
E- and D-type direct-coupled MESFETs that solve the problems of DCFL circuits using FETs, increase the operating margin of compound semiconductor integrated circuits against variations in threshold voltage, and enable the production of highly integrated compound semiconductor integrated circuits with high yield.
The purpose is to provide a logic circuit.

Means for Solving the Problems In order to solve the above problems, the inventor of the present invention conducted various studies and analyzed the most major mode of malfunction in GaAs integrated circuits of the DCFL circuit type. Note that what will be explained below is not limited to GaAs semiconductor integrated circuits.
This problem is common to other compound semiconductor integrated circuits, and the case of a GaAs semiconductor integrated circuit will be described as just one example.

Here, the basic gate circuit of the DCFL circuit shown in FIG. 1 will be considered. As mentioned above, MEs connected in multiple stages
The high level voltage of the output of each basic gate circuit of a DCFL circuit using SFETs is clamped by the rising voltage of a Schottky diode constituted by the gate portion of the MESFET.

On the other hand, the low level voltage of the output of each basic gate circuit is the power supply voltage ■. 0 divided by the on-resistance of the enhancement 1 FET 2 and the equivalent resistance of the depletion type FETI. The difference between the high level voltage and the low level voltage (approximately 0.6 V in a normal design) becomes the logic amplitude of this gate.

The logic threshold of this gate is the drain-source current of 1 ds (
Drain-source current 1 corresponding to Vg=O)
This is the gate voltage Vgs of the enhancement type FET 2 necessary for causing the voltage ds to flow through the enhancement type FET 2.

In addition, the switching speed of the logic gate circuit is faster as the current drive capability (the difference between the saturation current 1dss of FET2 and the saturation current 1dss of FET1) is larger, so the threshold voltage vth of the enhancement type FET2 is usually
As close to zero volts as possible (usually around +0.05 V)
is set to

Under the above conditions, a DCFL circuit using GaAs MESFET can be used for an LSI of several thousand gate class or higher.
In order to operate reliably, it is necessary to suppress variations in the threshold voltage of the MESFET to several tens of millivolts or less.

However, if the threshold voltage of the enhancement type FET is brought close to zero volts, where high-speed operation of GaAs integrated circuits is expected, the yield will deteriorate rapidly even if the dispersion is sufficiently suppressed to below the above value, making it difficult to put it into practical use. This was the biggest obstacle. This means that when the threshold voltage of the enhancement type FET becomes negative,
In other words, it was explained that this is because when a depletion type FET is used, the switching operation of the logic gate suddenly becomes incomplete.

However, as a result of detailed analysis by the inventor of the present invention, if the high-level voltage during off-state is maintained at around 0.7V, even if the enhancement type FET shifts to the depletion side, multiple throw connections will be possible. It has become clear that the gates that have been installed do not cause malfunctions. This was actually verified using the oscillation characteristics of the ring oscillator.

According to this idea, in an actual GaAs integrated circuit, the threshold voltage of the enhancement type FET is set near zero volts, and even if there is some variation in the threshold voltage, each gate circuit will not malfunction. Since this does not occur, sufficient manufacturing margin should be obtained.

Based on these findings, we further analyzed the failure of GaAs integrated circuits and found that the malfunction that occurs when the threshold voltage of the enhancement type FET becomes slightly negative is mainly due to the malfunction of the transfer gate when it is turned off. It became.

- The present invention was invented based on the above knowledge, and it separates the threshold voltages of the enhancement type FETs in the logic gate section and the transfer gate section, which were conventionally created with the same threshold voltage. , to ensure that the enhancement type FET in the transfer gate section is normally off.

That is, according to the present invention, a first enhancement type Schottky gate field effect transistor forming a switch element, and a depletion type second field effect transistor connected to the first field effect transistor and functioning as a load resistor. a Schottky gate field effect transistor,
an enhancement-type third Schottky gate field effect transistor connected to the first field effect transistor to constitute a transfer gate;
In the linear MMESFET logic circuit, the first field effect transistor is conductive at a gate voltage near zero, the second field effect transistor is reliably normally on, and the third field effect transistor is teeth,
The threshold voltages of the three field effect transistors are made to be different from each other so that they become conductive at a sufficiently high gate voltage.

In ED-type direct-coupled MESFET logic circuits, the third field-effect transistor that makes up the transfer gate does not conduct unless a sufficiently high gate voltage is applied, so it turns on and off at a voltage around 0. There is no fear that it will. Therefore, even if the threshold voltage of the first field effect transistor constituting the switch element is set to around 0■ to have a large current drive capability, the operation of the logic circuit will become unstable. High-speed and stable logic operation can be achieved.

ED type direct-coupled MES according to the present invention will be described below with reference to the attached drawings.
An example of a FET logic circuit will be described.

FIG. 2 is a schematic cross-sectional view of a semiconductor integrated circuit including a basic gate circuit and a transfer gate, which constitute the minimum unit of the ED type direct-coupled MESFET logic circuit shown in FIG. Note that the right half of FIG. 2 is a cross section along the line (a)-(b) of the left half.

In FIG. 2, reference number 10 is an insulating GaAs substrate, and the GaAs substrate 10 includes n-GaA
An s-region 12 is formed, and ohmic electrodes 16, 20 are formed on the n-GaAs region 12, as shown. The ohmic electrode 16 is drawn separately in the left half and right half of FIG. 2, but as mentioned above, the right half of FIG. ), and the ohmic electrode 16, which is shown separately in FIG. 2, is continuous.

A Schottky electrode 22 is provided between the ohmic electrodes 14 and 16, and a Schottky electrode 22 is provided between the ohmic electrodes 16 and 18.
A Schottky electrode 24 is provided between the ohmic electrodes 16 and 20, and a Schottky electrode 26 is provided between the ohmic electrodes 16 and 20.
is provided.

In the above configuration, the ohmic electrode 14, the Schottky electrode 22, the ohmic electrode 16, and the conductive region under these electrodes constitute one MESFET, and the ohmic electrode 16, the Schottky electrode 24, the ohmic electrode 18, and the conductive region below these electrodes constitute one MESFET. The conductive region below constitutes another MESFET, and the ohmic electrode 16, Schottky electrode 26, and ohmic electrode 20 and the conductive region under these electrodes constitute yet another MESFET.
It consists of

The impurity concentration in the n-GaAs region 28 below the Schottky electrode 24 is the highest, and the ohmic electrode 16, the Schottky electrode 24 and the ohmic electrode 18
and the conductive region beneath those electrodes.
The SFET is ensured to be a depletion type that is normally on.

On the other hand, the impurity concentration in the n-GaAs region below the Schottky electrode 26 is made the lowest, so that the ohmic electrode 16, the Schottky electrode 26, and the ohmic electrode 2
0 and the conductive regions under these electrodes.
The ESFET is ensured to be an enhancement type that is normally off.

The impurity concentration of the 71-GaAs region 30 under the Schottky electrode 22 is set to the impurity concentration between the above two regions, and the ohmic electrode 14, the Schottky electrode 22, the ohmic electrode 16, and the The MESFET formed by the lower conductive region is
It is designed to be an enhancement type with a nearby positive threshold voltage.

Also, the ohmic electrode 14 is grounded, the Schottky electrode 22 is used as an input electrode, and the ohmic electrode 1
6 and a Schottky electrode 24 are connected to each other, a driving voltage Von is applied to the ohmic electrode 18, the ohmic electrode 20 is used as an output, and the Schottky electrode 26 is used as a power source for transfer control signals such as clock pulses. used.

Thus, the integrated circuit shown in FIG.
A circuit consisting of FETI, 2 and 3 of type DCFL circuit is constructed. That is, the ohmic electrode 14, the Schottky electrode 22, the ohmic electrode 16, and the conductive region 30 under these electrodes constitute an n-channel enhancement type MESFETI which forms the switch element of FIG.
The ohmic electrode 16, the Schottky electrode 24, the ohmic electrode 18, and the conductive region 28 under these electrodes,
An n-channel depletion type MESFET 2 serving as a resistive load in FIG. 1 is configured, and an ohmic electrode 1
6. An n-channel enhancement type MES in which the Schottky electrode 26, the ohmic electrode 20, and the conductive region under these electrodes form the transfer gate of FIG.
It constitutes FET3.

By configuring as described above, in a DCFL circuit consisting of n-channel Ga 8sMESFET, the threshold voltage of the MESFET can be changed to the logic gate section enhancement type MESFET (switch element).
, logic gate section depletion type MESFET (load resistance), transfer gate section M E S' F E
The switch element MESFE is different for each T.
T conducts at a positive gate voltage near zero, and the load resistance MES
It is possible to ensure that the FET is normally on, and furthermore, that the ME'5FET of the transfer gate conducts at a gate voltage that is sufficiently higher than the low level voltage of the logic circuit.

By doing this, the MESFE of the switch element
T can obtain high current drive capability and turn on and off at high speed. On the other hand, MESF, which forms the transfer gate,
ET will not become conductive due to a low level voltage near 0, and no malfunction will occur when the transfer gate is off.

Furthermore, since the MESFET forming the load resistance is reliably set to 7-multiple on, there is no fear of malfunction such as turning off during operation.

Note that with the above configuration, the channel resistance of the MESFET that constitutes the transfer gate inserted in the path from the output of the logic gate to other human power becomes higher than that of the conventional one. However, according to calculations, the increase in resistance of the transfer gate section due to the above settings has only a slight effect on the speed of the GaAs integrated circuit.

As described above, the threshold voltages of the enhancement type FETs in the logic gate section and the transfer gate section, which were conventionally created with the same threshold voltage, are separated, and
By ensuring that the enhancement type FET in the transfer gate section is normally off, it is possible to reliably avoid malfunctions that have been a problem in the past.

Therefore, even if the threshold voltage of the logic gate enhancer (IFET) is set near zero volts, variations in the threshold voltage have almost no effect on the operation, so the operating margin is much greater than that of conventional ones. greatly,
High-speed GaAs integrated circuits can be produced with high yield.

The GaAs integrated circuit as described above can be formed, for example, as follows.

First, as shown in FIG. 3(a), a GaAs crystal substrate 1
For example, ions of Sl are ion-implanted at a dose of 1.2 XIO"cm-2 at an applied voltage of 50 KeV into the locations where the ohmic electrodes 16.18 and the Schottky electrodes 26 are to be formed on the n- A GaAs region 12 is formed.

Next, as shown in FIG. 3(b), ohmic electrodes 14 and 16 are formed in the n-type conductive region 12 of the GaAs crystal substrate 10, centering on the location where the Schottky electrode 22 is to be formed.
Further, Si is ion-implanted at an applied voltage of 50 eV to a dose of 1.4×1012.
Increase the concentration of Cm-2, n”-GaAs region 30
form.

Furthermore, as shown in FIG. 3(C), a GaAs crystal substrate 1
Furthermore, Si ions were ion-implanted at an applied voltage of 50 KeV into the n-type conductive region 12 of No. 0, centered around the location where the Schottky electrode 24 was to be formed, and extending to the locations where the ohmic electrodes 16 and 18 were to be formed. , the dose is 2 x 1012
The concentration is increased to cm-2 to form an n''-GaAs region 28.

After this, depending on the FET structure, ion implantation is selectively added under the ohmic electrode to lower the source resistance. After the above implantation is completed, annealing is performed at 800'C for 20 minutes to activate the implanted ions.

Thereafter, as shown in FIG. 2(d), an AuGe layer is placed on top of the conductive region 12 in ohmic contact with the GaAs.
i electrodes 14, 16, 18 and 20 are formed. This A
For example, uGeNi electrodes are made by first depositing Au-Ge, then depositing Ni, and then depositing GaA at 200 to 500°C.
It is formed by alloying with the s surface and then vapor depositing Au thereon.

Then, as shown in FIG. 2(e), over the conductive region 12 and between the ohmic electrodes 14, 16, 18 and 20, Ti/A is deposited in Schottky contact with the conductive region.
Form electrodes 22, 24 and 26 of u, respectively. The Ti/Au electrodes 22, 24 and 26 are formed by forming a photoresist film on the parts excluding the parts where the electrodes 22, 24 and 26 are to be formed using, for example, a vapor deposition lift-off method, and then forming a Ti/Au film on top of the photoresist film. is deposited, and then the photoresist film is removed and the Ti/Au deposited film other than the Ti/Au electrodes 22, 24 and 26 is removed together.

Ohmic electrode 1 of the semiconductor device formed as above
6 and the Schottky electrode 24, the ED type direct-coupled MESFET logic circuit of FIG. 2 is completed.

In the ED type direct-coupled MESFET logic circuit configured as described above, 1. The threshold voltage of the enhancement type MESFET that constitutes the switch element is +0.0
5 V, and depletion I that constitutes the load resistance
The threshold voltage of the MEsFET was -0.3V, and the threshold voltage of the enhancement type MEsFET constituting the transfer gate a was +0.3V.

In the above manufacturing process, the n-GaAs region 12 is formed by ion implantation, but it is also formed by molecular beam epitaxial growth (MBE) or metal organic chemical vapor deposition (MOCVD).
), etc.

In addition, in the case of a GaAs semiconductor integrated circuit, the metal material of the Schottky electrode that constitutes the gate electrode of the MESFET is as follows:
In addition to Ti, metals such as AI, Cr, Mo, and W, which have a large work function and form a Schottky barrier of sufficient height for the n-type conductive region, can also be used.

Furthermore, the impurity in the n-type conductive region is not only Si but also 5e
Donor materials for GaAs such as SSn, S, etc. can be used.

Above, an example in which the present invention is implemented using a GaAs semiconductor integrated circuit has been described, but the present invention also applies to InPSGaP, GaSb.

(It will be clear to those skilled in the art that the present invention can also be applied to other compound semiconductor integrated circuits such as nSb and InAs.

Effects of the Invention As is clear from the above explanation, the ED type direct-coupled MESFET logic circuit according to the present invention ensures that the enhancement type FET in the transfer section is normally off,
Since it is possible to reliably avoid the defective operation that was a problem in the past, the enhancement type FET in the logic gate section
Even if the threshold voltage is set near zero volts,
Since variations in threshold voltage have almost no effect on operation, the operating margin is much larger than that of conventional devices. Therefore, if the ED type direct-coupled MESFET logic circuit according to the present invention is used, compound semiconductor integrated circuits can be manufactured with high yield.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an ED type DCFL circuit to which the present invention can be applied, FIG. 2 is a cross-sectional view of an integrated circuit of an ED type DCFL circuit to which the present invention is implemented, and FIG. 3(a), 3), (C), (d), and (e) are diagrams illustrating an example of a method for manufacturing the ED type DCFL circuit of FIG. 2. [Main reference numbers] 1.4. - Depletion type FET. 2.3.5...Enhancement type FET.

Claims (3)

[Claims] (1) A first enhancement type Schottky gate field effect transistor forming a switch element, and a depletion type second Schottky gate electric field connected to the first field effect transistor and functioning as a load resistor. In an ED type direct-coupled MESFET logic circuit comprising an effect transistor and an enhancement type third Schottky gate field effect transistor connected to the first field effect transistor to constitute a transfer gate, the first field effect The transistor is conductive at a gate voltage near zero, the second field effect transistor is reliably normally on, and the third field effect transistor is conductive at a sufficiently high gate voltage. An ED type directly connected MESFET logic circuit characterized in that the threshold voltages of three field effect transistors are different from each other. (2) The three field effect transistors are n-channel type, and the threshold voltage of the first field effect transistor is higher than the threshold voltage of the second field effect transistor, and the threshold voltage of the third field effect transistor is higher than the threshold voltage of the second field effect transistor. The ED type direct-coupled MESFET logic circuit according to claim 1, characterized in that the voltage is a positive voltage in the vicinity of zero, which is lower than the threshold voltage of the field effect transistor. (3) The ED type direct-coupled MESFE according to claim (1) or (2), wherein the three field effect transistors are formed of a compound semiconductor.
T logic circuit.