JPS619737B2 - - Google Patents
Info
- Publication number
- JPS619737B2 JPS619737B2 JP55168582A JP16858280A JPS619737B2 JP S619737 B2 JPS619737 B2 JP S619737B2 JP 55168582 A JP55168582 A JP 55168582A JP 16858280 A JP16858280 A JP 16858280A JP S619737 B2 JPS619737 B2 JP S619737B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16858280A JPS5791535A (en) | 1980-11-29 | 1980-11-29 | Manufacture of semiconductor device |
US06/282,642 US4394196A (en) | 1980-07-16 | 1981-07-13 | Method of etching, refilling and etching dielectric grooves for isolating micron size device regions |
DE8686116670T DE3177250D1 (en) | 1980-07-16 | 1981-07-14 | METHOD FOR PRODUCING A SEMICONDUCTOR ARRANGEMENT WITH DIELECTRIC INSULATION ZONES. |
EP81105523A EP0044082B1 (en) | 1980-07-16 | 1981-07-14 | Method of manufacturing a semiconductor device comprising a dielectric insulating region |
DE8181105523T DE3177018D1 (en) | 1980-07-16 | 1981-07-14 | Method of manufacturing a semiconductor device comprising a dielectric insulating region |
EP86116670A EP0245538B1 (en) | 1980-07-16 | 1981-07-14 | Method for manufacturing a semiconductor device comprising dielectric isolation regions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16858280A JPS5791535A (en) | 1980-11-29 | 1980-11-29 | Manufacture of semiconductor device |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62001804A Division JPS62162343A (en) | 1987-01-09 | 1987-01-09 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5791535A JPS5791535A (en) | 1982-06-07 |
JPS619737B2 true JPS619737B2 (en) | 1986-03-25 |
Family
ID=15870721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16858280A Granted JPS5791535A (en) | 1980-07-16 | 1980-11-29 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5791535A (en) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6045037A (en) * | 1983-08-23 | 1985-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Substrate structure of semiconductor device and manufacture thereof |
JPS59121951A (en) * | 1982-12-28 | 1984-07-14 | Fujitsu Ltd | Semiconductor device and its manufacture |
JPS6045036A (en) * | 1983-08-23 | 1985-03-11 | Nippon Telegr & Teleph Corp <Ntt> | Substrate structure of semiconductor device and manufacture thereof |
US4980311A (en) * | 1987-05-05 | 1990-12-25 | Seiko Epson Corporation | Method of fabricating a semiconductor device |
US5371036A (en) * | 1994-05-11 | 1994-12-06 | United Microelectronics Corporation | Locos technology with narrow silicon trench |
US5895255A (en) * | 1994-11-30 | 1999-04-20 | Kabushiki Kaisha Toshiba | Shallow trench isolation formation with deep trench cap |
US5904539A (en) * | 1996-03-21 | 1999-05-18 | Advanced Micro Devices, Inc. | Semiconductor trench isolation process resulting in a silicon mesa having enhanced mechanical and electrical properties |
JP2000508474A (en) * | 1996-04-10 | 2000-07-04 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Semiconductor trench isolation with improved planarization method |
US5926713A (en) * | 1996-04-17 | 1999-07-20 | Advanced Micro Devices, Inc. | Method for achieving global planarization by forming minimum mesas in large field areas |
US5899727A (en) | 1996-05-02 | 1999-05-04 | Advanced Micro Devices, Inc. | Method of making a semiconductor isolation region bounded by a trench and covered with an oxide to improve planarization |
KR101575818B1 (en) | 2009-08-18 | 2015-12-08 | 삼성전자주식회사 | Method Of Forming Active Region Structure |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55108748A (en) * | 1979-02-14 | 1980-08-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device and manufacture thereof |
-
1980
- 1980-11-29 JP JP16858280A patent/JPS5791535A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55108748A (en) * | 1979-02-14 | 1980-08-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor integrated circuit device and manufacture thereof |
Also Published As
Publication number | Publication date |
---|---|
JPS5791535A (en) | 1982-06-07 |