JPS6196743A - Test for semiconductor device - Google Patents
Test for semiconductor deviceInfo
- Publication number
- JPS6196743A JPS6196743A JP21770784A JP21770784A JPS6196743A JP S6196743 A JPS6196743 A JP S6196743A JP 21770784 A JP21770784 A JP 21770784A JP 21770784 A JP21770784 A JP 21770784A JP S6196743 A JPS6196743 A JP S6196743A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- acceleration
- configuration
- sealing body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置特にキャビティを有する半導体装
置の加速度試験方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an acceleration testing method for a semiconductor device, particularly a semiconductor device having a cavity.
半導体装置の製造におじでは、品質管理ないし品質保証
の意味から、キャビティを有する半導体装置の加速j匙
試験を実施している。キャピテイを有する半導体装置と
は、半導体チップ・ポンディングワイヤなどの半導体素
子の構成要素を樹脂でかためず、半導体装置の容器と半
導体素子との間に空間的なすきまがあるものを員う0
従来、加速度試験を行なうには、先ず、第2図に示すよ
うにアダプタ2′内に半導体装置1を収容してから、前
記アダプタ2を第3図のロータ式加速度試験機のロータ
10の試料収容孔11に収めて、ロータ10を回転する
ことで、第2図に示す方向に加速度全印加していた。ア
ダプタ2は金属製の箱状体で、外形は試料収容孔11に
合わせ、内側の内壁形状は供試半導体装置1に合わせて
いる。試験の際は、アダプタ2に半導体装置1金入れ、
その上蓋・下蓋ケ単に重ねて接触保持させてから試料収
容孔11に入れる。したがって加速度試験のための半導
体装置1の着脱!−i極めて容易にま之迅速にできる利
点がある。In the manufacture of semiconductor devices, accelerated tests are carried out on semiconductor devices having cavities for the purpose of quality control or quality assurance. Semiconductor devices with cavities refer to those in which the components of semiconductor elements such as semiconductor chips and bonding wires are not hardened with resin, and there is a spatial gap between the semiconductor device container and the semiconductor elements. Conventionally, in order to perform an acceleration test, the semiconductor device 1 is first housed in an adapter 2' as shown in FIG. By placing the rotor 10 in the accommodation hole 11 and rotating the rotor 10, the entire acceleration was applied in the direction shown in FIG. The adapter 2 is a metal box-shaped body whose outer shape matches the sample accommodation hole 11 and whose inner wall shape matches the semiconductor device 1 under test. When testing, insert a semiconductor device into adapter 2,
The upper and lower lids are simply placed on top of each other and held in contact with each other, and then inserted into the sample accommodation hole 11. Therefore, attaching and detaching the semiconductor device 1 for acceleration testing! -i It has the advantage of being extremely easy and quick to learn.
従来の方法では、上記のよう[Ill定が迅速・容易に
できる利点があるが、パッケージ表面3とアダプタ内壁
面4との接触は、アダプタ2を半導体装置1のタイプご
とに寸法形状を定めるために、個々の半導体装置1の形
状バラツキがあると内壁面4とパッケージ表面3との接
触が不良になる。特にパッケージ表面3に凹凸かあると
、局部的に接触し、他の部分は接触しないことが多い。The conventional method has the advantage of being able to quickly and easily determine the Ill as described above, but the contact between the package surface 3 and the adapter inner wall surface 4 is difficult because the dimensions and shape of the adapter 2 are determined for each type of semiconductor device 1. Furthermore, if there are variations in the shape of the individual semiconductor devices 1, the contact between the inner wall surface 4 and the package surface 3 will be poor. In particular, if the package surface 3 is uneven, it often comes into contact locally and does not come into contact with other parts.
そのため加速度試験では、この局部に力が異常に加わり
パッケージ破損事故を生する欠点があった。Therefore, in the acceleration test, an abnormal force is applied to this local area, resulting in a package breakage accident.
また、加速度試験は、もともとキャビティ内のポンディ
ングワイヤ゛などに正確な力を与えるためのものである
から、上記の場合パッケージが破損にいたらなくても、
キャビライ内の構成要素に与える加速度の大きさにバラ
ツキが生じ誤った結果を与えることになる。In addition, since the acceleration test is originally intended to apply accurate force to the bonding wire inside the cavity, even if the package is not damaged in the above case,
This causes variations in the magnitude of the acceleration applied to the components within the cavity, giving erroneous results.
本発明の目的は、上記の欠点を除去し、半導体装置のパ
ッケージ表面の形状にバラツキかあ仁
っても、パッケージの破損がなく、しかもキヤとティ円
の栴#:要素に正確な所にの加速度を与えることのでき
る試験方法を提供することにある。It is an object of the present invention to eliminate the above-mentioned drawbacks, to prevent the package from being damaged even if the surface shape of the package of a semiconductor device varies, and to provide accurate positioning of the top and bottom of the circle. The purpose of this invention is to provide a test method that can give an acceleration of .
本発明の試験方法は、半導体装置全樹脂で封入し、加速
度試験機のロータの試料収容孔と略々等しい外形形状の
封入体となし、この封入体全前記試料収容孔に収めて加
速度試験を行なうものである。In the test method of the present invention, a semiconductor device is entirely encapsulated with resin to form an enclosure having an external shape approximately equal to the sample accommodation hole of the rotor of an acceleration tester, and the entire enclosure is placed in the sample accommodation hole to perform an acceleration test. It is something to do.
以下、本発明の一実施例につき説明する。第1図に、半
導体装置全樹脂で封入し几封入体5の断面図を示す。こ
の封入体5の形状は加速度試験機のロータ10の試料収
容孔11に合わせてつくっである。An embodiment of the present invention will be described below. FIG. 1 shows a cross-sectional view of an encapsulation body 5 in which a semiconductor device is completely encapsulated with resin. The shape of the enclosure 5 is made to match the sample receiving hole 11 of the rotor 10 of the acceleration testing machine.
図にみるように、半導体装置1のパッケージ表面3は全
面的に樹脂の部分に密着している。As shown in the figure, the entire package surface 3 of the semiconductor device 1 is in close contact with the resin portion.
この封入体5を試料収容孔11に収容し、加速度試験を
行なった場合、半導体装置1のパッケージ表面3の全面
に一様な力が加わり、局部的に異常な力が加わることが
ない。したがって実際に半導体装置1のパッケージ表面
6に凹凸があっても破損することはない。また半導体装
置1のキャビティ6FF3のボンディングワイヤ7、チ
ップ8などに及ぼす力は所定の加速度を与える。When this enclosure 5 is accommodated in the sample accommodation hole 11 and an acceleration test is performed, a uniform force is applied to the entire surface of the package surface 3 of the semiconductor device 1, and no abnormal force is applied locally. Therefore, even if the package surface 6 of the semiconductor device 1 actually has irregularities, it will not be damaged. Further, the force exerted on the bonding wire 7, chip 8, etc. of the cavity 6FF3 of the semiconductor device 1 gives a predetermined acceleration.
なお、封入する樹脂材としては、加速度試験の後に、電
気的特性試験と外観検資とのために有機解削、酸等で容
易に溶解するものを使用する。As for the resin material to be encapsulated, one that is easily dissolved by organic cutting, acid, etc. is used for the electrical property test and appearance inspection after the acceleration test.
本発明によれば、加速度試験に際し、半導体装置のパッ
ケージには一様な力が働くので、パッケージが破損する
ことがない。またキャビティ内の半導体素子の構成要素
には一様な所定の力が加わり試験結果の信頼性が高い。According to the present invention, a uniform force is applied to the package of a semiconductor device during an acceleration test, so that the package is not damaged. Further, a uniform predetermined force is applied to the components of the semiconductor element within the cavity, increasing the reliability of the test results.
その他、従来のように、各柚形状の半導体装置に備えて
多数のアダフタを用意する必要がない。試料収容孔の形
状に適合するモールド型の−dヲ用意するだけでよい0
′In addition, there is no need to prepare a large number of adapters for each yuzu-shaped semiconductor device, unlike the conventional method. All you need to do is prepare a mold that matches the shape of the sample receiving hole.
′
5g1図は、本発明の一実施例における封入体の断面図
、第2図は、従来の方法においてアダプタに半導体装置
を組込んだ状態を示す断面図、第3図は加速度試験機の
ロータの断面図である。
1・・・半導体装置、 2・・・アダプタ、3・・
・半導体装置のパッケージ表面、4・・・アダプタの内
壁面、 5・・・封入体、10・・・ロータ、
11・・・試料収容孔、6・・・キャビティ、
7山ボンテイングワイヤ、8・・・チップ。Figure 5g1 is a cross-sectional view of an enclosure in an embodiment of the present invention, Figure 2 is a cross-sectional view showing a state in which a semiconductor device is incorporated into an adapter in a conventional method, and Figure 3 is a cross-sectional view of a rotor of an acceleration testing machine. FIG. 1... Semiconductor device, 2... Adapter, 3...
- Package surface of semiconductor device, 4... Inner wall surface of adapter, 5... Encapsulation body, 10... Rotor,
11... Sample accommodation hole, 6... Cavity,
7 strand bonding wire, 8...chip.
Claims (1)
供試品をロータの試料収容孔に収め、ロータを回転して
加速度を印加する方式において、前記半導体装置を樹脂
で封入してなる試料収容孔と略々等しい外形形状の封入
体を、前記供試品として用いることを特徴とする半導体
装置の試験方法。As an acceleration test for semiconductor devices with cavities,
In a method in which a sample is placed in a sample accommodation hole of a rotor and the rotor is rotated to apply acceleration, an encapsulation body made of the semiconductor device sealed with resin and having an external shape approximately the same as the sample accommodation hole is placed in the sample accommodation hole of the rotor. A method for testing a semiconductor device characterized by using it as a sample.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21770784A JPS6196743A (en) | 1984-10-17 | 1984-10-17 | Test for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21770784A JPS6196743A (en) | 1984-10-17 | 1984-10-17 | Test for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6196743A true JPS6196743A (en) | 1986-05-15 |
Family
ID=16708474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP21770784A Pending JPS6196743A (en) | 1984-10-17 | 1984-10-17 | Test for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6196743A (en) |
-
1984
- 1984-10-17 JP JP21770784A patent/JPS6196743A/en active Pending
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