JPS6195556A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6195556A
JPS6195556A JP21615784A JP21615784A JPS6195556A JP S6195556 A JPS6195556 A JP S6195556A JP 21615784 A JP21615784 A JP 21615784A JP 21615784 A JP21615784 A JP 21615784A JP S6195556 A JPS6195556 A JP S6195556A
Authority
JP
Japan
Prior art keywords
concentration
phosphorus
film
protective film
protection film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21615784A
Other languages
Japanese (ja)
Inventor
Takeo Yoshimi
吉見 武夫
Hideo Sakai
秀男 坂井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP21615784A priority Critical patent/JPS6195556A/en
Publication of JPS6195556A publication Critical patent/JPS6195556A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve reliability and prevent deterioration in element characteristic through suppression of generation of cracks in protection film by forming said protection to be formed on a metal wiring layer in such a manner that the characteristic changes in the thickness direction. CONSTITUTION:A protection film 8 is given the structure that concentration of phosphorus (a) contained changes in the direction of thickness. For example, the minimum phosphorus concentration is set to about 0.5mol% and the maxi mum concentration is set to 6mol%. Such constitution can be attained, for example, on the occasion of forming the protection film 8 by the CVD method, the concentration of PH3 gas to be mixed to the SiH4 gas is changed continuous ly with the time. It is desirable that the phosphorus concentration (a) changes at least in a period in the direction of thickness. Thereby, since the protection film 8 has the structure that PSG thin films in different phosphorus concentrations are integrally formed in multilayer structure, the film as a whole has the structure that the soft portion by high phosphorus concentration and the hard portion by low phosphorus concentration are integrated.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に金属配線の保護膜を改
良した半導体装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a protective film for metal wiring is improved.

〔背景技術〕[Background technology]

IC,LSI等の半導体装置は半導体基板の主面上に形
成した素子間や外部接続用の電極パッド間を電気的に接
続するために金属配線層1通常ではl配線層が用いられ
る。そして、このAl配線層を外部の湿気、熱、外力等
から保護するために、A−e配線層上には7アイナルパ
ウシペーシ!ンと称される保護膜が形成されており、一
般にはりんを含有したSiガラス、即ちPSG膜が利用
されている。
2. Description of the Related Art In semiconductor devices such as ICs and LSIs, a metal wiring layer 1 (usually a metal wiring layer) is used to electrically connect between elements formed on the main surface of a semiconductor substrate and between electrode pads for external connection. In order to protect this Al wiring layer from external moisture, heat, external force, etc., 7-inch aluminum wiring layer is placed on the A-e wiring layer. A protective film called phosphor is formed, and Si glass containing phosphorus, that is, a PSG film is generally used.

ところで、この保護膜について本発明者等が種々の検討
を行なったところ、熱履歴を受けた半導体装置では保護
膜に多数のクラックが発生し、このクラックを通して湿
気(水分)JP空気等がA7配線層に侵入してこれを腐
蝕させる等、半導体装置の信頼性を低下させる事故が生
じ易いことが明らかになった。そして、このクラックの
発生原因としては熱履歴によってA2配線層が熱膨張、
収縮する際にPSG膜がその熱膨張率の違いによってこ
れに追従することができず、この差に基づいて発生され
る内部応力がPSG膜にクラックを生しさせるものと考
えられる。
By the way, the present inventors conducted various studies regarding this protective film, and found that in semiconductor devices that had undergone thermal history, many cracks occurred in the protective film, and through these cracks, moisture (moisture), air, etc. It has become clear that accidents that degrade the reliability of semiconductor devices, such as penetrating layers and corroding them, are likely to occur. The cause of this crack is the thermal expansion of the A2 wiring layer due to thermal history.
It is thought that when the PSG film contracts, it is unable to follow it due to the difference in coefficient of thermal expansion, and the internal stress generated based on this difference causes cracks to occur in the PSG film.

、−のため、本発明者等はPSG膜に係わる要件を変え
なからPSG膜の性質を検討したところ。
, -, the present inventors examined the properties of the PSG film without changing the requirements related to the PSG film.

含有させろりんの濃度が低いと硬性になり、りんの度を
高めると柔軟性の性質になることが判明した。また、生
成速度を変化させることによっても特性が変化すること
が判明した。そして、この結果に基ついて珪々の膜質の
保護膜の信頼性を検討したところ、PSG膜のりん濃度
変化の場合、りん濃度を高くすればクラックの発生は低
減されるが、外部より侵入した湿気水分によって大量の
りんが溶出しリン酸となってA2バッド(ワイヤボンデ
ィング用開口部)を腐蝕させるおそれのあることが判明
した。なお、絶縁膜形成技術を詳しく述べである列とし
ては、日経マグロウヒル社発行、8村エレクトロニクス
別冊「マイクロデバイセズ」、昭和58年8月22日発
行、P、124〜P、]28かある。
It was found that when the concentration of phosphorus contained is low, it becomes hard, and when the degree of phosphorus is increased, it becomes flexible. It has also been found that the characteristics change by changing the production rate. Based on this result, we examined the reliability of a protective film with a uniform quality, and found that when the phosphorus concentration of a PSG film changes, increasing the phosphorus concentration reduces the occurrence of cracks; It has been found that a large amount of phosphorus is eluted by moisture and becomes phosphoric acid, which may corrode the A2 pad (wire bonding opening). Incidentally, a column describing the insulating film forming technology in detail is ``Micro Devices,'' published by Nikkei McGraw-Hill, Inc., 8mura Electronics Special Edition, August 22, 1980, P, 124-P, ]28.

〔発明の目的〕[Purpose of the invention]

本発明の目的は保護膜におけるクラックの発生を抑制し
て信頼性の向上を図ると共に、素子特性を劣化させるこ
とのない半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device that suppresses the occurrence of cracks in a protective film, improves reliability, and does not cause deterioration of device characteristics.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示されろ発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
A brief overview of typical inventions disclosed in this application is as follows.

すなわち、金属配線層上に形成する保護膜を厚さ方向に
その特性が変化されるよう構成することにより、各特性
の組合せの総合作用によって金属配線層の変形に伴なう
保護膜のクラック発生を抑止し、かつ信頼性の向上を図
るものである。
In other words, by configuring the protective film formed on the metal wiring layer so that its characteristics change in the thickness direction, cracks in the protective film due to deformation of the metal wiring layer can be prevented by the overall effect of the combination of each characteristic. The aim is to prevent this and improve reliability.

〔実施例1〕 第1図は本発明をMO8型半導体装置に適用した例であ
り、7リコン基板1の主面上にはフィールド酸化膜2.
ゲート酸化膜3を形成し、その上にゲート電極4を形成
している。また、主面には不純物(ひ素等)を拡散して
ソース・ドレイン領域5.5を形成し、前記ゲート電極
4とでMOSトランジスタを構成している。前記ゲート
電極ないしソース・ドレイン領域5.5上にはシリコン
酸化膜等の層間絶縁膜6を形成し、しかる上でソース・
ドレイン領域5,5にスルーホールヲ形成し、ここにA
2配線層7.7を形成してMOSトランジスタの電気接
続を行なっている。そして、この上K P S Gから
なる保護膜(パノシベーショノ膜)8を全面にわたって
形成し、前記A2配線11巧7を覆っている。
[Embodiment 1] FIG. 1 shows an example in which the present invention is applied to an MO8 type semiconductor device, in which a field oxide film 2.
A gate oxide film 3 is formed, and a gate electrode 4 is formed thereon. In addition, impurities (such as arsenic) are diffused on the main surface to form source/drain regions 5.5, which together with the gate electrode 4 constitute a MOS transistor. An interlayer insulating film 6 such as a silicon oxide film is formed on the gate electrode or source/drain region 5.5, and then the source/drain region 5.5 is formed.
Through holes are formed in the drain regions 5, 5, and A is formed here.
Two wiring layers 7.7 are formed to electrically connect the MOS transistors. Then, a protective film (panosivation film) 8 made of KPSG is formed over the entire surface to cover the A2 wiring 11 7.

この保護膜8は第2回圧その一部を特性図と共に模式的
に示すよ5IC1その厚さ方向に含有するりんの濃度を
変化させた構成としている。りん濃度は最低で0.5m
o1%程度、最大で6mo1%の範囲であり、本例では
正弦波曲線に類似の周期的な変化率(θ度/Rさ)で0
度を変化させている。
This protective film 8 has a structure in which the concentration of phosphorus contained in 5IC1 is varied in the thickness direction, as shown schematically with a characteristic diagram of a part of the second pressure. Phosphorus concentration is at least 0.5m
The range is about 1%, maximum is 6mo1%, and in this example, it is 0 with a periodic rate of change (θ degree/R degree) similar to a sine wave curve.
The degree is changing.

このような構成は、か]えばCVD法により保護膜8を
形成する場合にはS i H4ガスに混合させるPH。
Such a configuration is such that, for example, when forming the protective film 8 by the CVD method, the pH is mixed with the S i H4 gas.

ガスの濃度(供給計)を時間の昼過と共に連続的に変化
させればよい。なお、りん濃度の変化は、七の厚さ方向
に少な(とも1周期の変化が生じるように構成すること
が好ましい。
It is sufficient to continuously change the gas concentration (supply meter) as the day progresses. Note that it is preferable to configure the structure so that the change in phosphorus concentration is small (in one cycle in each direction).

以上の構成によれば、保護膜8はりん濃度の異なるPS
G薄膜が多層にかつ一体に構成された状態とされている
ため、膜全体としては高りん濃度による柔軟性の部分と
、低りん濃度によろ硬性の部分とが一体化された構成と
される。したがって、下層のA2配線層7が熱膨張され
或いは収縮されても、この変形は高りん濃度の柔軟性に
より吸収され、或いは小さな変形力は低りん濃度の硬性
によりこれを押え込み変形を拘束する。この結果、保護
膜8での内部応力は抑制されてクランクの発生が抑止さ
れ、信頼性が向上されることになる。
According to the above configuration, the protective film 8 is made of PS with different phosphorus concentrations.
Since the G thin film is made up of multiple layers and an integral structure, the film as a whole has a structure in which a flexible part due to a high phosphorus concentration and a stiff part due to a low phosphorus concentration are integrated. . Therefore, even if the lower A2 wiring layer 7 is thermally expanded or contracted, this deformation is absorbed by the flexibility of the high phosphorus concentration, or a small deformation force is suppressed by the hardness of the low phosphorus concentration, thereby restraining the deformation. As a result, internal stress in the protective film 8 is suppressed, the occurrence of cranks is suppressed, and reliability is improved.

なお、保護膜8全体としてのりん濃度(平均濃度)は従
来と同程度以下に抑制できるため、素子に悪(・影響を
与えることはない。
In addition, since the phosphorus concentration (average concentration) of the protective film 8 as a whole can be suppressed to the same level or lower than that of the conventional method, it does not adversely affect the device.

〔実施例2〕 第3図は本発明の他の実施例の要部をその特性と共に示
す図である。この保護膜8Aは、同図に模式的に示すよ
うに、PSGのりん0度を傾斜状態に変化させており、
この結果、保護膜8Aの厚さ方向はもとより平面方向に
もつん濃度が変化される構成となる。このような保護膜
8Aは1例えば第5図に示すように、CVDチャ/バl
Oの内部上方に夫々PH,ガス噴出量の異なるノズル1
1a〜lliを並設し、この下方位置で可動テーブル1
2上に載置され1こシリコン基板1をゆつ(つと一方向
に移動させなからCVD成膜を行なう方法により形成で
きる。勿論、テーブル12の移動速度や方向、更に同一
動作を複数回繰返丁等により、様々な濃度分布のものを
得ることができる。
[Embodiment 2] FIG. 3 is a diagram showing the main parts of another embodiment of the present invention together with its characteristics. As schematically shown in the same figure, this protective film 8A changes the 0 degree phosphorus of PSG to an inclined state,
As a result, the protective film 8A has a configuration in which the concentration changes not only in the thickness direction but also in the planar direction. For example, as shown in FIG.
Nozzles 1 with different pH and gas ejection amount are installed in the upper part of the inside of O.
1a to lli are arranged side by side, and the movable table 1 is placed in this lower position.
The silicon substrate 1 placed on the table 12 can be formed by CVD film formation without moving in one direction. Various concentration distributions can be obtained by returning the book etc.

本実施例においても下層のAJ?配線層7の変形をりん
濃度特性により吸収ないし拘束でき、特に本例では厚さ
方向のみならず平面方向にも吸収。
In this embodiment as well, the lower layer AJ? Deformation of the wiring layer 7 can be absorbed or restrained by the phosphorus concentration characteristics, and in particular, in this example, it is absorbed not only in the thickness direction but also in the planar direction.

拘束を行なうことができるので、クラックの発生を更に
有効に抑止できる。
Since the restraint can be performed, the occurrence of cracks can be more effectively suppressed.

〔効 果〕〔effect〕

(f)PSGからなる保護膜のりん濃度を厚さ方向に変
化させて特性を厚さ方向に変化させているので、へ2配
線層における変形を柔軟部では吸収し、硬性部では抑制
でき、これにより保護膜の内部応力の発生を防止し、ク
ラックの発生を抑止して信頼性の向上が達成できる。
(f) Since the phosphorus concentration of the protective film made of PSG is changed in the thickness direction to change the characteristics in the thickness direction, deformation in the F2 wiring layer can be absorbed in the flexible part and suppressed in the hard part. This prevents the generation of internal stress in the protective film, inhibits the generation of cracks, and improves reliability.

(2)  りん濃度を厚さ方向のみならず平面方向にも
変形させているので、A[配線層の平面に対しても有効
に吸収、拘束を行なうことができ、クラックの抑止効果
を高めろことができろ。
(2) Since the phosphorus concentration is changed not only in the thickness direction but also in the plane direction, it can effectively absorb and restrain the plane of the wiring layer, increasing the effect of suppressing cracks. Be able to do that.

(3)  りん濃度を最高、最低の間で変化させている
ので、保股膜全体としてのりん含有量を抑制でき、集子
等を劣化させることはない。
(3) Since the phosphorus concentration is varied between the highest and lowest levels, the phosphorus content of the protective film as a whole can be suppressed, and the adhesive etc. will not deteriorate.

以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは−・5までもない。たとえば、りん濃度
は厚さ方向又は平面方向に段階的に変化させろようにし
てもよい。
Although the invention made by the present inventor has been specifically explained above based on examples, it is understood that the present invention is not limited to the above-mentioned examples, and that various changes can be made without departing from the gist of the invention. Not even 5. For example, the phosphorus concentration may be changed stepwise in the thickness direction or in the planar direction.

〔利用分野〕[Application field]

以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるM QS型半導体装
置のPSG膜に適用した場合fついて説明したが、それ
忙限定されるものではなく、バイポーラ型半導体装置に
も適用できろ。また、PSG以外に限らずプラズマSi
xNyやプラズマ5ixOyの6膜にも適用でき、これ
らのN、Oの0度を変化すればよい。更に6膜の含有濃
度を変化させる外に、膜の生成速度を変化させることK
より、膜の特性を変化させるよう忙してもよい。
In the above explanation, the invention made by the present inventor is mainly applied to a PSG film of an MQS type semiconductor device, which is the background field of application. It can also be applied to type semiconductor devices. In addition, not only PSG but also plasma Si
It can also be applied to six films of xNy and plasma 5ixOy, and the 0 degrees of these N and O can be changed. Furthermore, in addition to changing the concentration of the film, the rate of film formation can also be changed.
The properties of the membrane may also be altered.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明を適用した一実施例の断面図、第2図は
要部をその特性と共に拡大図示した模式図、 第3図は他の実施例の第2図と同様の図。 第4図は第3図実施例構造の製造方法を説明するための
装置[略図である。 1・・シリコン基板、4・・ゲート電極、5・・ソース
・ドレイン領域、6・・・層間絶縁膜、7・・・人!配
線層、8.8A 保護膜、IO−・チャンバ、lla〜
lli ・・ノズル、12・・可動テーブル。 代理人 9F埋士  高 橋 明 夫1− ・第   
1  図 第  2  図 ? /′
FIG. 1 is a cross-sectional view of one embodiment to which the present invention is applied, FIG. 2 is a schematic diagram showing an enlarged view of the main part along with its characteristics, and FIG. 3 is a diagram similar to FIG. 2 of another embodiment. FIG. 4 is a schematic diagram of an apparatus for explaining the manufacturing method of the structure of the embodiment shown in FIG. 1...Silicon substrate, 4...Gate electrode, 5...Source/drain region, 6...Interlayer insulating film, 7...People! Wiring layer, 8.8A Protective film, IO-・chamber, lla~
lli...nozzle, 12...movable table. Agent 9F Burial Officer Akio Takahashi 1-・No.
1 Figure 2? /′

Claims (1)

【特許請求の範囲】 1、Al等の金属配線層上に保護膜を形成してなる半導
体装置において、前記保護膜の特性をその厚さ方向に変
化させた構成としたことを特徴とする半導体装置。 2、特性は平面方向にも変化されてなる特許請求の範囲
第1項記載の半導体装置。 3、保護膜はりんを含有したSiガラスであり、リンの
含有濃度を変化させてなる特許請求の範囲第1項又は第
2項記載の半導体装置。 4、保護膜は生成速度を変化させてなる特許請求の範囲
第1項ないし第3項のいずれかに記載の半導体装置。
[Claims] 1. A semiconductor device comprising a protective film formed on a metal wiring layer such as Al, characterized in that the characteristics of the protective film are varied in the direction of its thickness. Device. 2. The semiconductor device according to claim 1, wherein the characteristics are also changed in the plane direction. 3. The semiconductor device according to claim 1 or 2, wherein the protective film is Si glass containing phosphorus, and the concentration of phosphorus is varied. 4. The semiconductor device according to any one of claims 1 to 3, wherein the protective film is formed at a rate of change.
JP21615784A 1984-10-17 1984-10-17 Semiconductor device Pending JPS6195556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21615784A JPS6195556A (en) 1984-10-17 1984-10-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21615784A JPS6195556A (en) 1984-10-17 1984-10-17 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6195556A true JPS6195556A (en) 1986-05-14

Family

ID=16684183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21615784A Pending JPS6195556A (en) 1984-10-17 1984-10-17 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6195556A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0417373A (en) * 1990-05-11 1992-01-22 Toshiba Corp Manufacture of nonvolatile semiconductor memory
JPH07130731A (en) * 1993-10-29 1995-05-19 Nec Corp Semiconductor device and its manufacturing method and apparatus
US5716890A (en) * 1996-10-18 1998-02-10 Vanguard International Semiconductor Corporation Structure and method for fabricating an interlayer insulating film
US5770469A (en) * 1995-12-29 1998-06-23 Lam Research Corporation Method for forming semiconductor structure using modulation doped silicate glasses
JP2006332356A (en) * 2005-05-26 2006-12-07 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0417373A (en) * 1990-05-11 1992-01-22 Toshiba Corp Manufacture of nonvolatile semiconductor memory
JPH07130731A (en) * 1993-10-29 1995-05-19 Nec Corp Semiconductor device and its manufacturing method and apparatus
US5770469A (en) * 1995-12-29 1998-06-23 Lam Research Corporation Method for forming semiconductor structure using modulation doped silicate glasses
US5716890A (en) * 1996-10-18 1998-02-10 Vanguard International Semiconductor Corporation Structure and method for fabricating an interlayer insulating film
JP2006332356A (en) * 2005-05-26 2006-12-07 Fuji Electric Device Technology Co Ltd Semiconductor device and its manufacturing method

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