JPS6194360U - - Google Patents
Info
- Publication number
- JPS6194360U JPS6194360U JP1984178468U JP17846884U JPS6194360U JP S6194360 U JPS6194360 U JP S6194360U JP 1984178468 U JP1984178468 U JP 1984178468U JP 17846884 U JP17846884 U JP 17846884U JP S6194360 U JPS6194360 U JP S6194360U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- terminals
- strobe
- level
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
Landscapes
- Semiconductor Integrated Circuits (AREA)
Description
第１図はこの考案の基本的な回路図、第２図は
第１の実施例を示す平面図、第３図は第２の実施
例を示す平面図である。 １…集積回路、２，３…ストローブ端子、４…
電源端子、５…論理接地端子、６〜９…回路導体
、１０〜１２…外部端子、１３，１４…内部端子
、１５〜１８…接続部、２０…回路基板。
第１の実施例を示す平面図、第３図は第２の実施
例を示す平面図である。 １…集積回路、２，３…ストローブ端子、４…
電源端子、５…論理接地端子、６〜９…回路導体
、１０〜１２…外部端子、１３，１４…内部端子
、１５〜１８…接続部、２０…回路基板。
Claims (1)
- “Ｈ”レベルでアクテイブになる第１のストロ
ーブ端子、“Ｌ”レベルでアクテイブになる第２
のストローブ端子“Ｈ”レベルの入力が与えられ
る第１の端子及び“Ｌ”レベルの入力が与えられ
る第２の端子とを備えている集積回路と、前記各
端子に接続される回路導体を備えている回路基板
とからなり、前記回路基板に、前記第１、２の端
子に接続されてあつて、外部から“Ｈ”，“Ｌ”
レベルの入力が与えられる第１、２の外部端子と
、前記各ストローブ端子に接続される第１、２の
内部端子と、信号入力が外部から与えられる第３
の外部端子とを設けてなり、かつ前記第３の外部
端子を前記第１、２の内部端子に、使用しようと
するストローブ端子に応じて選択的に接続自在と
するとともに、前記内部端子のうち前記第３の外
部端子に接続されない内部端子を前記第１または
第２の外部端子に接続自在としてなる集積回路用
接続装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984178468U JPS6194360U (ja) | 1984-11-24 | 1984-11-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984178468U JPS6194360U (ja) | 1984-11-24 | 1984-11-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6194360U true JPS6194360U (ja) | 1986-06-18 |
Family
ID=30736031
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984178468U Pending JPS6194360U (ja) | 1984-11-24 | 1984-11-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6194360U (ja) |
-
1984
- 1984-11-24 JP JP1984178468U patent/JPS6194360U/ja active Pending
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