JPS6194360U - - Google Patents

Info

Publication number
JPS6194360U
JPS6194360U JP1984178468U JP17846884U JPS6194360U JP S6194360 U JPS6194360 U JP S6194360U JP 1984178468 U JP1984178468 U JP 1984178468U JP 17846884 U JP17846884 U JP 17846884U JP S6194360 U JPS6194360 U JP S6194360U
Authority
JP
Japan
Prior art keywords
terminal
terminals
strobe
level
external
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1984178468U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1984178468U priority Critical patent/JPS6194360U/ja
Publication of JPS6194360U publication Critical patent/JPS6194360U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第1図はこの考案の基本的な回路図、第2図は
第1の実施例を示す平面図、第3図は第2の実施
例を示す平面図である。 1…集積回路、2,3…ストローブ端子、4…
電源端子、5…論理接地端子、6〜9…回路導体
、10〜12…外部端子、13,14…内部端子
、15〜18…接続部、20…回路基板。

Claims (1)

    【実用新案登録請求の範囲】
  1. “H”レベルでアクテイブになる第1のストロ
    ーブ端子、“L”レベルでアクテイブになる第2
    のストローブ端子“H”レベルの入力が与えられ
    る第1の端子及び“L”レベルの入力が与えられ
    る第2の端子とを備えている集積回路と、前記各
    端子に接続される回路導体を備えている回路基板
    とからなり、前記回路基板に、前記第1、2の端
    子に接続されてあつて、外部から“H”,“L”
    レベルの入力が与えられる第1、2の外部端子と
    、前記各ストローブ端子に接続される第1、2の
    内部端子と、信号入力が外部から与えられる第3
    の外部端子とを設けてなり、かつ前記第3の外部
    端子を前記第1、2の内部端子に、使用しようと
    するストローブ端子に応じて選択的に接続自在と
    するとともに、前記内部端子のうち前記第3の外
    部端子に接続されない内部端子を前記第1または
    第2の外部端子に接続自在としてなる集積回路用
    接続装置。
JP1984178468U 1984-11-24 1984-11-24 Pending JPS6194360U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984178468U JPS6194360U (ja) 1984-11-24 1984-11-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984178468U JPS6194360U (ja) 1984-11-24 1984-11-24

Publications (1)

Publication Number Publication Date
JPS6194360U true JPS6194360U (ja) 1986-06-18

Family

ID=30736031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984178468U Pending JPS6194360U (ja) 1984-11-24 1984-11-24

Country Status (1)

Country Link
JP (1) JPS6194360U (ja)

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