JPS6441974U - - Google Patents
Info
- Publication number
- JPS6441974U JPS6441974U JP13670687U JP13670687U JPS6441974U JP S6441974 U JPS6441974 U JP S6441974U JP 13670687 U JP13670687 U JP 13670687U JP 13670687 U JP13670687 U JP 13670687U JP S6441974 U JPS6441974 U JP S6441974U
- Authority
- JP
- Japan
- Prior art keywords
- hybrid integrated
- integrated circuit
- lead terminal
- circuit pattern
- tip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001285 shape-memory alloy Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Multi-Conductor Connections (AREA)
- Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案の実施例の説明図、第2図は従
来の実施例の説明図を示す。 1……基板、2……孔、3……リードピン、3
′……リードピンの先端部、3″……突部、4…
…回路パターン。
来の実施例の説明図を示す。 1……基板、2……孔、3……リードピン、3
′……リードピンの先端部、3″……突部、4…
…回路パターン。
Claims (1)
- 回路パターンと、該回路パターンの入・出力用
リード端子を有する混成集積回路基板において、
前記リード端子の先端部に形状記憶合金を使用し
たことを特徴とする混成集積回路用リード端子。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13670687U JPS6441974U (ja) | 1987-09-07 | 1987-09-07 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13670687U JPS6441974U (ja) | 1987-09-07 | 1987-09-07 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6441974U true JPS6441974U (ja) | 1989-03-13 |
Family
ID=31397465
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13670687U Pending JPS6441974U (ja) | 1987-09-07 | 1987-09-07 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6441974U (ja) |
-
1987
- 1987-09-07 JP JP13670687U patent/JPS6441974U/ja active Pending