JPS6193909A - Synchronous rectifire circuit for differential transformer - Google Patents

Synchronous rectifire circuit for differential transformer

Info

Publication number
JPS6193909A
JPS6193909A JP21539384A JP21539384A JPS6193909A JP S6193909 A JPS6193909 A JP S6193909A JP 21539384 A JP21539384 A JP 21539384A JP 21539384 A JP21539384 A JP 21539384A JP S6193909 A JPS6193909 A JP S6193909A
Authority
JP
Japan
Prior art keywords
differential transformer
voltage signal
circuit
output
transformer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21539384A
Other languages
Japanese (ja)
Inventor
Tadashi Furuta
直史 古田
Kunio Oi
大井 邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SANKUSU KK
Panasonic Industrial Devices SUNX Co Ltd
Original Assignee
SANKUSU KK
Sunx Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SANKUSU KK, Sunx Ltd filed Critical SANKUSU KK
Priority to JP21539384A priority Critical patent/JPS6193909A/en
Publication of JPS6193909A publication Critical patent/JPS6193909A/en
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

PURPOSE:To eliminate the need for an intricate phase adjusting operation and to simplify construction without decreasing the detection accuracy of a differential transformer and deteriorating the linearity by subjecting the secondary output of the differential transformer to waveform shaping to obtain a synchronizing signal. CONSTITUTION:This circuit is so arranged as to obtain the synchronizing signal S13 in accordance with the voltage signal S4 from the secondary coil 4 of the differential transformer 1 and therefore the phases of the synchronizing signal S13 and the voltage signal S1 outputted from the secondary side of the differential transformer 1 can be made always to coincide regardless of the frequency of an oscillator 6, the number of coil turns of the transformer 1, the position of a core 5 and temp. conditions. The need for the phase adjusting operation is therefore eliminated at all times, a delay circuit is omitted and the construction is simplified. The distortion of the output voltage signal S14 by a rectifier circuit 14 is obviated and the deterioration in the detection accuracy by the transformer 1 and the linearity thereof is prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、直線センサとして有用な差動変圧器の二次側
出力を整流するための回路、特には上記二次側出力を同
期信号tこ同期させて整流するようにした差動変圧器用
の同期整流回路に関する。
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a circuit for rectifying the secondary side output of a differential transformer useful as a linear sensor, and particularly to a circuit for rectifying the secondary side output of a differential transformer useful as a linear sensor. The present invention relates to a synchronous rectifier circuit for a differential transformer that performs synchronized rectification.

〔従来技術〕[Prior art]

差動変圧器は良く知られているように、高精度直線性、
出力安定度9分解能等の電気的特性並びに耐久性その他
の機械的特性が非常に良好であるため、直線変位センサ
としてきわめて広範囲に使用されている。しかして差動
変圧器の二次側出力を整流するための回路の一例として
、従来よシ第3図に示す如く構成された同期整流回路が
供されている。
As is well known, differential transformers have high precision linearity,
Since it has very good electrical properties such as output stability and 9 resolution, as well as durability and other mechanical properties, it is used extremely widely as a linear displacement sensor. As an example of a circuit for rectifying the secondary output of a differential transformer, a synchronous rectifier circuit constructed as shown in FIG. 3 has conventionally been provided.

即ち、第5図において、1は差動変圧器で、これは良く
知られているように一次伺1コイル2.二次側コイル3
.4及びコア5よ)成ろ。6は発振器で、これは第4図
(d)に示すような正弦波状の交8及び9は増幅器7の
出力を受ける夫々バッファ及びインバータバッファであ
る。1oは上記バッファ8及びインバータバッファ9の
出力を整流する整流回路で、第3図ではモデル的に示す
が、セレクト端子Sに対する入力がマイナスレベルのと
きに接点10Bをオンしてバッファ8からの出力を通過
させ、セレクト端子Sに対する入力がプラスレベルのと
きに接点1[)bをオンしてインバータバッファ9から
の出力を通過させる。一方、11は発振器6か゛らの電
圧信号S6を所定時間だけ遅延させる遅延回邸、12は
この遅延回路1−1の出力を矩形波に整形して前記整流
回路10のセレクト端子Sに与える波形整形回路である
That is, in FIG. 5, 1 is a differential transformer, which, as is well known, has a primary coil, 1 coil, and 2. Secondary coil 3
.. 4 and Core 5) Become. Reference numeral 6 denotes an oscillator, which has a sinusoidal waveform as shown in FIG. 4(d). Reference numerals 8 and 9 represent a buffer and an inverter buffer, respectively, which receive the output of the amplifier 7. 1o is a rectifier circuit that rectifies the outputs of the buffer 8 and the inverter buffer 9, which is shown as a model in FIG. When the input to the select terminal S is at a positive level, contact 1[)b is turned on to allow the output from the inverter buffer 9 to pass. On the other hand, 11 is a delay circuit that delays the voltage signal S6 from the oscillator 6 by a predetermined time, and 12 is a waveform shaping circuit that shapes the output of this delay circuit 1-1 into a rectangular wave and applies it to the select terminal S of the rectifier circuit 10. It is a circuit.

しかして斯かる構成において、発振器6からの交流電圧
信号86が差動変圧器1の一次側コイル2に与えられる
と、その差動変圧器1の二次側からコア5の位置に応じ
た値の電圧信号S1(第4図(a)に波形を示す)が出
力され、その電圧信号S1が増;陥器7によって増幅さ
れる。このため、バッファ8からは上記増幅信号と同位
相の電圧信号8a(第4図(b)#照)が出力され、イ
ンバータバッファ9からは電圧信号S8と逆位相の電圧
信号Sp(第4図(0) 参照)が出力される。一方、
遅延回路11は、発振M6からの電圧信号S6を所定時
間遅延させた電圧信号511(第4図(e)参照)を波
形整形回路12に与え、この波形整形回#812は、入
力された電圧信号S11のゼロクロスポイントで反転す
る第4図(f)に示すような矩形波状の同期信号S+z
を出力して整流回路10のセレクト端子f子Sに与える
。この結果、整流回路1Qは、同期信号S12がローレ
ベルの期間にバッファ8からの電圧信号S8を通過させ
ると共に、同期信号812がハイレベルの期間にインバ
ータバッファ9からの電圧信号S?を通過させるように
なりその整流回路10から第4図(g)に示すような直
流E圧信号81oが出力される。そして斯様な直流電圧
信号810のレベルに基づいてコ15の変位置を知るこ
とができる。
However, in such a configuration, when the AC voltage signal 86 from the oscillator 6 is applied to the primary coil 2 of the differential transformer 1, a value corresponding to the position of the core 5 from the secondary side of the differential transformer 1 is generated. A voltage signal S1 (the waveform of which is shown in FIG. 4(a)) is output, and the voltage signal S1 is amplified by the amplifier 7. Therefore, the buffer 8 outputs a voltage signal 8a having the same phase as the amplified signal (see FIG. 4(b)), and the inverter buffer 9 outputs a voltage signal Sp having the opposite phase to the voltage signal S8 (see FIG. 4(b)). (0)) is output. on the other hand,
The delay circuit 11 provides a voltage signal 511 (see FIG. 4(e)) obtained by delaying the voltage signal S6 from the oscillation M6 by a predetermined time to the waveform shaping circuit 12, and this waveform shaping circuit #812 converts the input voltage A synchronization signal S+z in the form of a rectangular wave as shown in FIG. 4(f) which is inverted at the zero cross point of the signal S11.
is output and applied to the select terminal f of the rectifier circuit 10. As a result, the rectifier circuit 1Q passes the voltage signal S8 from the buffer 8 while the synchronizing signal S12 is at a low level, and the voltage signal S? from the inverter buffer 9 while the synchronizing signal 812 is at a high level. The rectifying circuit 10 outputs a DC E pressure signal 81o as shown in FIG. 4(g). Based on the level of the DC voltage signal 810, the position of the motor 15 can be known.

ところが上記従来構成では、同期信号812を差動変圧
器1の一次側(具体的には発振器6)から得ろようにな
されているため、□以下に述べる欠点があった。即ち、
差動変圧器1の一次側雷圧(電圧信号86)と二次側電
圧(電圧信号S1)との間には必らず位相差(通常二次
側電圧が進み位相となる)が生ずるものであり、斯かる
位相差は。
However, in the conventional configuration described above, since the synchronizing signal 812 is obtained from the primary side of the differential transformer 1 (specifically, from the oscillator 6), there is a drawback described below. That is,
A phase difference always occurs between the primary side lightning voltage (voltage signal 86) and the secondary side voltage (voltage signal S1) of the differential transformer 1 (normally, the secondary side voltage leads the phase). And the phase difference is.

発振器6の局波数及び差動変圧器1のコイJl/ターン
数に依存して変化する。このため従来構成では、上記位
相差を遅延回&S11によって調整して同期信号812
及び電圧信号S1の各位相を一致させるようしている。
It changes depending on the local wave number of the oscillator 6 and the number of coils Jl/turns of the differential transformer 1. Therefore, in the conventional configuration, the phase difference is adjusted by the delay circuit &S11, and the synchronization signal 812 is
and the respective phases of the voltage signal S1 are made to match.

しかしながら、この構成では上記位相調整作莱が煩雑に
なる不具合があるばかりか、二すリ延回路11を余分に
必要として構造の6雑化を招く。寸だ、電圧信号S1及
び86間の位相差は、コア5の位置の変化、温度変動及
び発振器6の発振周期変動等の後発的要因によっても変
化するものであるが、従来構成では斯様な後発的要因に
よる電圧信号S1及び86間の位相差を吸収することが
できない。このため実際には、差動変圧器1の二次側電
圧信号81−と同期信号812との間に第4図ぽ示すよ
うな位相ずれが生じ、その結果として直流電圧信号8+
oの波形が歪んで差U;119圧器1による検出開度の
低下及びその直線性の悪化等を招く。
However, this configuration not only has the disadvantage that the phase adjustment operation is complicated, but also requires two extra extension circuits 11, resulting in a complicated structure. Indeed, the phase difference between the voltage signals S1 and 86 also changes due to subsequent factors such as changes in the position of the core 5, temperature fluctuations, and fluctuations in the oscillation cycle of the oscillator 6. The phase difference between the voltage signals S1 and 86 due to subsequent factors cannot be absorbed. Therefore, in reality, a phase shift occurs between the secondary voltage signal 81- of the differential transformer 1 and the synchronization signal 812 as shown in FIG.
The waveform of o is distorted, resulting in a decrease in the opening degree detected by the pressure device 1 and deterioration of its linearity.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、差小す変圧器の二次側出力を同期信号
に同期させて整流する場合であっても、差動変圧器の検
出精度の低下及びその直線性の悪化を招く虞がない2井
に、従来必要であった煩雑な位相調j7作朶゛を不要に
でき、さらには構造の簡単化をも図シ得る等の効果を奏
する差動変圧器用の同期整流回路を提供するにある。
An object of the present invention is to prevent the detection accuracy of the differential transformer from decreasing and its linearity to deteriorate even when the secondary output of the differential transformer is rectified in synchronization with a synchronizing signal. To provide a synchronous rectifier circuit for a differential transformer, which can eliminate the need for complicated phase adjustment operations conventionally required, and can also simplify the structure. It is in.

〔発明の要約〕[Summary of the invention]

本発明は差動変圧器の二次側出力を同期信号に同期させ
て整流する同期整流回路において、前記同期信号を、差
動変圧器の二次側出力を波形整形することにより得るよ
うにしたものである。
The present invention provides a synchronous rectifier circuit that rectifies the secondary output of a differential transformer in synchronization with a synchronous signal, in which the synchronous signal is obtained by waveform shaping the secondary output of the differential transformer. It is something.

〔実施例〕〔Example〕

以下、本発明の一実施例について第1図及び第2図を参
照しながら説明する。但し、第3図と同一部分について
は、これと同一符号を付すことによルその説明を省略す
る。
An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. However, the same parts as those in FIG. 3 are designated by the same reference numerals and the explanation thereof will be omitted.

第1図において、13は波形整形回路で、これは差動変
圧器1の二次側出力特には一方の二次コイル4からの電
圧信号84(第2図(d)参照)を受けるように設けら
れ、入力された電圧信号S4のゼロクロスポイントでに
転する第2図(e)に示すような矩形波状の同期信号S
15を出力して整流回路14のセレクト端子8に与える
。上記整流回路14は、第1図ではモデル的に示すが、
セレクト端子Sに対する入力がプラスレベルのときに接
点14aをオンしてバッファ8からの出力を通過させ、
セレクト端子Sに対する入力がマイナスレベルのときに
接点14bをオンしてインバータバッファ9からの出力
を通過させる。
In FIG. 1, 13 is a waveform shaping circuit, which receives a voltage signal 84 (see FIG. 2(d)) from the secondary side output of the differential transformer 1, particularly from one of the secondary coils 4. A synchronizing signal S in the form of a rectangular wave as shown in FIG. 2(e) changes at the zero cross point of the input voltage signal S4.
15 is output and applied to the select terminal 8 of the rectifier circuit 14. The rectifier circuit 14 is shown as a model in FIG.
When the input to the select terminal S is at a positive level, the contact 14a is turned on to allow the output from the buffer 8 to pass;
When the input to the select terminal S is at a negative level, the contact 14b is turned on to allow the output from the inverter buffer 9 to pass.

上記r4成によれば、同期信号815を差動変圧器1の
二次側コイル4からの電圧信号S4に基づいて得るよう
にしている°から、この同期信号813伎び差動変圧器
1の二次側から出力される電圧信号S+(第2図(a)
参照)の各位相を、発振器6の周波数、差動変圧器1の
コイルターン数、コア5の位置及び温度条件の如何に拘
らず常に一致させることができる。このため、従来必要
であった位相調整作泥を不要にできると、共に、遅延回
路11(第5図参照)を省略することができて構造を簡
単化できる。また、整流回路14による出力電圧信号5
14(@2図げ)参照)が従来のように歪むことがなく
、差動変圧器1による検出精度並び、にその直線性の悪
化を招く虞がないものである。
According to the above r4 configuration, since the synchronizing signal 815 is obtained based on the voltage signal S4 from the secondary coil 4 of the differential transformer 1, the synchronizing signal 813 and the voltage signal S4 of the differential transformer 1 are Voltage signal S+ output from the secondary side (Figure 2 (a)
) can always be matched regardless of the frequency of the oscillator 6, the number of coil turns of the differential transformer 1, the position of the core 5, and the temperature conditions. Therefore, the phase adjustment process that was conventionally necessary can be eliminated, and the delay circuit 11 (see FIG. 5) can be omitted, simplifying the structure. In addition, the output voltage signal 5 from the rectifier circuit 14
14 (see @2 Figure)) is not distorted as in the conventional case, and there is no risk of deterioration of the detection accuracy or linearity of the differential transformer 1.

尚、第2図(b) 、 (C)は夫々バッファ8からの
電圧信号8 s 、インバータバッファ9からの電圧信
号S?を示す。
Incidentally, FIGS. 2(b) and 2(C) show the voltage signal 8s from the buffer 8 and the voltage signal S? from the inverter buffer 9, respectively. shows.

〔発明の効果〕〔Effect of the invention〕

本発明によれば以上の説明によって明らかなように、差
動変圧器の二次側出力を同期信号に同期させて整流する
同期整流回路において、前記差動変圧器の二次側出力を
波形整形することにより前ができるものであシ、これに
よって差動変圧器の検出精度の低下及びその直線性の悪
化を招く虞がないと共に、煩雑な位相調整作秦を不要に
でき、さらには構造の簡単化をも図シ得るものである。
According to the present invention, as is clear from the above description, in a synchronous rectifier circuit that rectifies the secondary output of a differential transformer in synchronization with a synchronous signal, the secondary output of the differential transformer is waveform-shaped. This eliminates the risk of lowering the detection accuracy of the differential transformer and deteriorating its linearity, eliminates the need for complicated phase adjustment operations, and further improves the structure. This also allows for simplification.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明の一実施例を示すもので、第
1図は電気的構成図、第2図は第1図中の各部の出力波
形図である。また、第3図及び第4図は従来例を示すも
ので、第3図は第1図相当図、第4図は第3図中の各部
の出力波形図である。 図中、1は差動変圧器、6は発振器、8はバッファ、9
はインバータバッファ、13は波形整形回路、14は整
流回路を示す。 BirH人 サンクス株式会社 第 1 図 第 2 図
1 and 2 show one embodiment of the present invention, FIG. 1 is an electrical configuration diagram, and FIG. 2 is an output waveform diagram of each part in FIG. 1. Further, FIGS. 3 and 4 show conventional examples, with FIG. 3 being a diagram corresponding to FIG. 1, and FIG. 4 being an output waveform diagram of each part in FIG. In the figure, 1 is a differential transformer, 6 is an oscillator, 8 is a buffer, and 9
13 represents an inverter buffer, 13 represents a waveform shaping circuit, and 14 represents a rectifier circuit. BirH person Thanks Co., Ltd. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、差動変圧器の二次側出力を同期信号に同期させて整
流するものにおいて、前記差動変圧器の二次側出力を波
形整形することにより前記同期信号を発生する波形整形
回路を設けたことを特徴とする差動変圧器用の同期整流
回路。
1. In a device that synchronizes and rectifies the secondary side output of a differential transformer with a synchronizing signal, a waveform shaping circuit is provided that generates the synchronizing signal by waveform shaping the secondary side output of the differential transformer. A synchronous rectifier circuit for a differential transformer.
JP21539384A 1984-10-15 1984-10-15 Synchronous rectifire circuit for differential transformer Pending JPS6193909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21539384A JPS6193909A (en) 1984-10-15 1984-10-15 Synchronous rectifire circuit for differential transformer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21539384A JPS6193909A (en) 1984-10-15 1984-10-15 Synchronous rectifire circuit for differential transformer

Publications (1)

Publication Number Publication Date
JPS6193909A true JPS6193909A (en) 1986-05-12

Family

ID=16671569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21539384A Pending JPS6193909A (en) 1984-10-15 1984-10-15 Synchronous rectifire circuit for differential transformer

Country Status (1)

Country Link
JP (1) JPS6193909A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527817A (en) * 2002-05-24 2005-09-15 アサイラム リサーチ コーポレーション Linear variable differential transformer with digital electronics
JP4824132B1 (en) * 2011-03-01 2011-11-30 大建工業株式会社 Method for producing translucent cosmetic material

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50118224A (en) * 1974-03-04 1975-09-16
JPS543372B2 (en) * 1975-10-09 1979-02-22
JPS57197418A (en) * 1981-05-29 1982-12-03 Anritsu Corp Displacement measuring device
JPS58178925A (en) * 1982-04-13 1983-10-20 アルプス電気株式会社 Method of producing keyboard switch

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50118224A (en) * 1974-03-04 1975-09-16
JPS543372B2 (en) * 1975-10-09 1979-02-22
JPS57197418A (en) * 1981-05-29 1982-12-03 Anritsu Corp Displacement measuring device
JPS58178925A (en) * 1982-04-13 1983-10-20 アルプス電気株式会社 Method of producing keyboard switch

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005527817A (en) * 2002-05-24 2005-09-15 アサイラム リサーチ コーポレーション Linear variable differential transformer with digital electronics
JP4824132B1 (en) * 2011-03-01 2011-11-30 大建工業株式会社 Method for producing translucent cosmetic material

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