JPS6193695A - Generation of lattice-like wire pattern - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a method for forming a lattice-like wiring pattern that can automatically form a non-conducting pattern in a lattice-like wiring pattern that becomes the power supply wiring or ground wiring of an electronic circuit board. It is related to.

[Conventional technology]

Electronic circuit boards generally have multilayer wiring configurations, and grid patterns with pinches of several millimeters are relatively often used for power supply wiring or ground wiring. When forming component insertion holes, connection pin insertion holes, etc. in such a grid wiring pattern, it is necessary to remove a part of the grid wiring pattern so as not to contact the wiring pattern.

In recent years, wiring patterns for electronic circuit boards like this are created using computers, and in the case of grid-like wiring patterns, data such as the width and spacing of the grid-like wiring patterns are stored in files. By reading out the data and inputting information defining the outer periphery, a lattice-like wiring pattern according to the successive data is formed within the defined outer periphery and displayed on the display device. Then, an input operation is performed on the displayed lattice-like wiring pattern to form a non-conducting pattern corresponding to a component insertion hole or the like.

When a desired wiring pattern is formed, the data is added to an artwork device or the like to automatically create a film that serves as an exposure mask for forming the wiring pattern.

[Problem that the invention seeks to solve]

Inputting a non-conducting pattern to a grid wiring pattern is as follows:
This is done using an input device such as a keyboard or mouse, but
Make sure that the insertion hole etc. and the grid wiring pattern do not come into contact with each other.
The specified distance must be maintained.

Therefore, it is necessary to erase the grid sides of the grid wiring pattern in relation to the dimensions of the non-conducting pattern to be formed, which is a complicated task along with specifying the placement position. Met. In addition, when there are a large number of such non-conducting patterns, there is a drawback that the working time for forming each non-conducting pattern by hollowing it out within the lattice-like wiring pattern becomes extremely long.

The present invention aims to improve the above-mentioned conventional drawbacks.

[Means for solving problems]

The grid-like wiring pattern forming method of the present invention assumes that the width of the grid-like wiring pattern is zero, and performs a process of enlarging a non-conducting pattern to be formed within the grid-like wiring pattern.
The size is expanded to the sum of 1/2 the width of the lattice-like wiring pattern and the minimum interval required between the non-conducting pattern and the wiring pattern. Then, by erasing the lattice sides of the lattice wiring pattern within the enlarged non-conductive pattern, a lattice wiring pattern is formed in which the non-conductive pattern is hollowed out and has a predetermined distance from the wiring pattern. It is something.

[Effect]

The value obtained by adding 1/2 the width of the lattice wiring pattern and the minimum interval required between the non-conductive pattern and the wiring pattern is added to the non-conductive pattern and expanded, and this expanded non-conductive pattern is This method erases the lattice sides of the lattice wiring pattern in the conductive pattern to create a lattice wiring pattern with a predetermined interval between the wiring pattern and the non-conductive pattern, and it also involves enlarging the non-conducting pattern, Grid side deletion processing can be achieved by applying enlargement and reduction processing in graphic processing, deletion processing for the shape type, etc., and non-conductive patterns can be automatically created just by manually inputting the peripheral data. It is possible to create a lattice-like wiring pattern with inner cutouts.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a processor (CPU), 2 is a memory (MEM) having areas A, B, and C as well as an area for storing programs, etc.
3, 4.5 is an input/output control device (Ilo), 6 is an input device such as a keyboard, 7 is a display device, and 8 is an artwork that performs exposure, development, etc. according to pattern data and outputs a film such as a mask pattern. The device 9 is a file device. The file device 9 stores circuit pattern data including data on the wiring width and pitch of the lattice wiring pattern, non-conducting pattern data, and the like.

First, under the control of the processor 1, circuit pattern data is read from the file device 9 and
Store in. Next, outer circumference data specifying the outer circumference of the lattice wiring pattern is inputted from the input device 6. Processor 1 stores this outer circumferential data in area B of memory 2. Then, the processor 1 reads the outer circumference data and the lattice wiring pattern data of the circuit pattern data, generates a lattice pattern within the designated outer circumference, and stores it in the area B of the memory 2. , is applied to the display device 7 via the input/output control device 4. Thereby, a predetermined pinch grid pattern is displayed on the display device 7 within the designated outer periphery.

Next, the processor 1 reads out one piece of non-conducting pattern data from the area A of the memory 2, performs an enlargement process on this non-conducting pattern, and stores it in the area C of the memory 2. This enlargement process assumes that the line width of the lattice wiring pattern is zero.
Grid pattern wiring pattern width) x (1/2) + (minimum spacing between conductors) - Additional dimension This can be realized by processing similar to enlarging, enlarging, and reducing processing in graphic processing.

Next, the processor 1 identifies the overlap between the lattice patterns read from areas B and C of the memory 2 and the enlarged non-conducting pattern. In addition, the non-conductive pattern
Since the data also includes position data specifying the arrangement position, it is possible to easily identify a case where a portion of the enlarged non-conducting pattern overlaps with the lattice pattern. Then, the lattice sides of the lattice pattern within the non-conductive pattern are erased. In this case, the lattice sides that intersect with the outer periphery of the enlarged non-conductive pattern are also erased. This lattice edge erasing process can be realized by a process similar to the erasing process of a figure-shaped part in graphic processing. The lattice pattern whose lattice sides have been erased is stored in area B of the memory 2.

If a non-conducting pattern remains in area A of the memory 2, one of the remaining non-conducting patterns is read out and subjected to the same enlargement process as described above and the process of erasing the lattice sides of the lattice pattern stored in area B. and stores it in the memory 2 area.

The process of erasing grid edges may result in grid edges that are completely separated from the surrounding grid pattern. In such a case, processing for making the pattern continuous with the surrounding grid patterns by adding grid sides, or processing for changing the arrangement position of the non-conducting pattern, etc., will be performed.

When all the processing for the non-conducting pattern is completed, the area B of the memory 2 stores the data of the lattice-like wiring pattern in which the non-conducting pattern has been hollowed out. Data input/output control device 5
When outputted to the artwork device 8 via the lattice wiring pattern data, a lattice wiring pattern film of an electronic circuit board is created and outputted by exposing and developing a pattern according to the lattice wiring pattern data.

FIG. 2 and FIG. 3 are explanatory diagrams of the grid-like wiring pattern, and as the outer circumferential data of the grid-like wiring pattern, a (x+
,y+)+b(x+,yj),c(xm.

yJ ), d (xm, yi+), e (
xi, yh), f (X=, )', ) are input from the input device 6 or the like. It is also possible to employ means for directly inputting this outer circumference data onto the display screen of the display device using a light pen or the like. Also, in the case of the outer circumference of a rectangle,
It is good to input the coordinate information of four points.

Also, the lattice wiring pattern data is read out as described above, and a lattice pattern with a predetermined pitch is formed within the designated outer periphery a-=f. Also, the hatched Pl, P2.
P3 indicates a non-conductive pattern, and these non-conductive patterns PI, P2 . In P3, the data is sequentially read from area A of the memory 2 and enlarged as shown by the chain line. As mentioned above, this enlarging process assumes that the line width of the lattice wiring pattern is zero, and requires 1/2 of the width of the lattice wiring pattern and the space between the wiring pattern and the non-conducting pattern. The non-conductive pattern p1. P2. It performs processing added to P3.

By erasing the lattice sides of the lattice pattern within the enlarged non-conducting pattern, that is, within the chain lines, hollow regions Nl, N2 . This results in a lattice-like wiring pattern in which N3 is formed. Then, the non-conducting pattern and the wiring pattern have a small distance (both of which are equal to the sum of 1/2 the width of the lattice wiring pattern and the minimum necessary distance), so that parts etc. This also results in a wiring pattern that does not cause short-circuit accidents.

Furthermore, depending on the arrangement position of the non-conductive pattern, the grid-like wiring pattern may be separated into islands. This can be detected by sequentially scanning the created lattice-like wiring pattern and checking whether there is a wiring pattern surrounded by a hollow area, so it can be detected that the wiring pattern is separated into islands. If detected, a grid side is added or the placement position of the non-conductive pattern is changed.

FIG. 4 shows an example of a flowchart of an embodiment of the present invention, in which circuit pattern data is read from the file device 9, stored in area A of the memory 2, and outer circumference data specifying the outer circumference is input to the input device. Input from 6th grade. Thereby, lattice wiring pattern data is read from area A, and a lattice pattern is generated within the designated outer periphery.

Next, the non-conductive pattern data is read from area A of the memory 2, the non-conductive pattern is enlarged, and the lattice sides in the enlarged non-conductive pattern are erased to form a lattice with hollows formed. The wiring pattern data is stored in area B of the memory 2.

It is determined whether or not a non-conductive pattern remains in area A of the memory 2, and if it remains, the non-conductive pattern is read out, and if it does not remain, the formation of the lattice wiring pattern is completed. Then, the data is transferred to the artwork device 8, and a lattice wiring pattern film is created and output.

〔Effect of the invention〕

As explained above, the present invention assumes that the width of the lattice wiring pattern is zero, and creates a non-conductive pattern for inserting a component to be formed in the lattice wiring pattern by adjusting the width of the lattice wiring pattern. The lattice of the lattice-like wiring pattern in this enlarged non-conducting pattern is enlarged to the sum of 1/2 of By performing the process of erasing the sides, a lattice-like wiring pattern is formed by cutting out the inside of the non-conducting pattern. Just by inputting the outer circumference data of the lattice-like wiring pattern, the desired circuit pattern is automatically created. Since it is possible to form a hollow corresponding to a non-conductive pattern in an electronic circuit board, there is an advantage that a lattice-like wiring pattern for an electronic circuit board can be formed easily and in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 and FIG.
The figure is an explanatory diagram of the process of creating a lattice-like wiring pattern, and FIG. 4 shows an example of a flowchart of an embodiment of the present invention. 1 is the processor (CPU), 2 is the memory (MEM)
3 to 5 are input/output control devices (Ilo), 6 is an input device,
7 is a display device, 8 is an artwork device, and 9 is a file device.

Claims (1)

[Claims] In a method for creating a grid-like wiring pattern for an electronic circuit board in which a non-conducting pattern is hollowed out, the width of the grid-like wiring pattern is regarded as zero, and the non-conducting pattern to be formed within the grid-like wiring pattern is The pattern is enlarged to a size equal to the sum of 1/2 of the width of the lattice-like wiring pattern and the minimum interval required between a non-conductive pattern and a wiring pattern, and within the enlarged non-conductive pattern. A method for forming a lattice-like wiring pattern, comprising erasing lattice sides of the lattice-like wiring pattern to cut out non-conducting patterns.