CN115392175B - Circuit design error processing method, device and medium - Google Patents
Circuit design error processing method, device and medium Download PDFInfo
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- G06F30/30—Circuit design
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Abstract
The application relates to the field of power electronics and discloses a circuit design error processing method, a device and a medium, wherein the method comprises the following steps: acquiring each first design file and judging whether each first design file is an error file or not; if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information; creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file to acquire the second design file; the second design file is incorporated into the master circuit file to obtain the target circuit. According to the scheme, element information and coordinate information of the sub-circuit in the error file are extracted, and the information is written into a second design file established based on the main circuit file, so that the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, and working waste of a developer is caused is prevented. Thereby improving the circuit development efficiency.
Description
Technical Field
The present disclosure relates to the field of power electronics, and in particular, to a method, an apparatus, and a medium for processing circuit design errors.
Background
With the development of power electronics technology, printed circuit boards (Printed Circuit Board, PCBs) are widely used in applications such as large servers. As the complexity of the circuit increases, the size and scale of the PCB circuit increases. In order to accelerate the development speed, it is generally required that many people cooperatively develop the PCB circuit board. Fig. 1 is a schematic diagram of a common circuit board, as shown in fig. 1, in the development process, an overall PCB circuit board is divided into a plurality of sub-circuits, each sub-circuit is distributed to each developer, and the sub-circuits completed by each developer are combined on the same PCB board.
Because the iteration speed of the circuit in the PCB is high, the versions of the circuit files are more, and a developer may acquire the files of the wrong version in the process of distributing the circuit, and design the circuit based on the files of the wrong version. However, currently, a general development tool (e.g., cadence) cannot merge different versions of sub-circuit files, resulting in waste of work of developers and further affecting the circuit development efficiency.
Therefore, how to provide a design method of a PCB circuit board to prevent the work of a developer from being ineffective due to task distribution errors is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The purpose of the application is to provide a circuit design error processing method, a device and a medium, so that the work inefficiency of a developer caused by task file distribution errors in the circuit design process is prevented, and the development efficiency is improved.
In order to solve the above technical problems, the present application provides a circuit design error processing method, including:
acquiring first design files and judging whether each first design file is an error file or not;
if the error file is the error file, analyzing the error file to acquire sub-circuit coordinate information and sub-circuit element information;
creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file;
and the second design file is integrated into the main circuit file to obtain a target circuit, wherein the target circuit is a complete circuit corresponding to the circuit design requirement.
Preferably, before the step of obtaining each first design file, the method further includes:
acquiring a circuit design requirement;
dividing the target circuit into a main circuit and at least one target sub-circuit according to the circuit design requirement;
and sending each target sub-circuit to each developer to complete task allocation.
Preferably, the determining whether the error file exists in each of the first design files includes:
judging whether the first design file and the main circuit file can be combined or not;
if the first design files cannot be combined, determining that the current first design files are error files.
Preferably, before the step of creating the second design file according to the sub-circuit coordinate information, the method further includes:
judging whether the difference degree between a sub-circuit in the error file and the target sub-circuit is lower than a difference degree threshold value;
and if the difference degree is lower than the difference degree threshold value, executing the step of creating a second design file according to the sub-circuit coordinate information.
Preferably, the creating the second design file according to the sub-circuit coordinate information includes:
determining a target sub-circuit of a region corresponding to the sub-circuit coordinate information in the main circuit file, and importing the target sub-circuit into an initial file;
and initializing the initial file to obtain the second design file.
Preferably, the degree of difference includes a first degree of difference for characterizing a difference in the manner of connection of the circuit and a second degree of difference for characterizing the circuit element.
Preferably, the writing the sub-circuit element information into the second design file to obtain the second design file includes:
determining difference elements of a sub-circuit in the error file and the target sub-circuit;
and writing the difference element into the second design file.
In order to solve the above technical problem, the present application further provides a circuit design error processing apparatus, including:
the judging module is used for acquiring each first design file and judging whether each first design file is an error file or not;
the analysis module is used for analyzing the error file to acquire sub-circuit coordinate information and sub-circuit element information if the error file is the error file;
the first acquisition module is used for creating a second design file according to the sub-circuit coordinate information and the main circuit file and writing the sub-circuit element information into the second design file;
and the second acquisition module is used for merging the second design file into the main circuit file to acquire a target circuit, wherein the target circuit is a complete circuit corresponding to the circuit design requirement.
In order to solve the above technical problem, the present application further provides another circuit design error processing apparatus, including a memory for storing a computer program;
and the processor is used for realizing the steps of the circuit design error processing method when executing the computer program.
In order to solve the above technical problem, the present application further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the circuit design error processing method.
The application provides a circuit design error processing method, which comprises the following steps: acquiring each first design file and judging whether each first design file is an error file or not; if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information; creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file to acquire the second design file; the second design file is incorporated into the master circuit file to obtain the target circuit. Therefore, in the application scheme, when the fact that the first design file sent by the developer is the error file is detected, element information and coordinate information of the sub-circuit in the error file are extracted, and the information is written into the second design file established based on the main circuit file, so that the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, and working waste of the developer is caused is prevented. Thereby improving the circuit development efficiency.
In addition, the application also provides a circuit design error processing device and a medium, which correspond to the method and have the same effects.
Drawings
For a clearer description of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a conventional circuit board;
FIG. 2 is a flow chart of a circuit design error handling method according to an embodiment of the present disclosure;
FIG. 3 is a block diagram of a circuit design error handling apparatus according to an embodiment of the present disclosure;
fig. 4 is a block diagram of another circuit design error handling apparatus according to an embodiment of the present application.
Detailed Description
The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments herein without making any inventive effort are intended to fall within the scope of the present application.
The core of the application is to provide a circuit design error processing method, a device and a medium, so that the work invalidation of a developer caused by the task file distribution error is prevented in the circuit design process, and the development efficiency is improved.
In a circuit development application scenario, in order to ensure development efficiency, a development task needs to be divided into a plurality of modules, and each developer is responsible for development work of each module. Because of the large number of versions of the circuit files, developers may acquire the files of the wrong versions during the process of distributing the circuits, and design the circuits based on the files of the wrong versions. However, currently, a general development tool (for example Cadence) cannot merge sub-circuit files with different versions, so that circuit element information in an error file cannot be effectively used, resulting in waste of workload of a developer and even affecting development progress and development efficiency of a circuit. In order to solve the problem, the application provides a circuit design error processing method, wherein a development supervisor determines a target circuit according to design requirements in advance, divides the target circuit into a plurality of sub-circuits, and distributes the sub-circuits to corresponding developers. When the first design file sent by the developer is detected to be an error file, element information and coordinate information of a sub-circuit in the error file are extracted, and the information is written into a second design file established based on the main circuit file, so that the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, and working waste of the developer is caused is prevented. Thereby improving the circuit development efficiency.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description.
Fig. 2 is a flowchart of a circuit design error processing method according to an embodiment of the present application, and as shown in fig. 2, the circuit design error processing method includes:
s10: and acquiring each first design file, and judging whether each first design file is an error file or not.
In a specific implementation, after a manager obtains a development requirement, if the development requirement is to design a new circuit, determining the technical requirement of each module in the target circuit according to the development requirement, determining a design scheme and a circuit schematic diagram according to the development requirement and technical requirement information of each module, and determining wiring and component layout modes according to the circuit schematic diagram to determine the circuit of each module. Finally, the circuits of all the modules are combined to a main circuit to obtain a target circuit meeting the design requirement; if the design requirement is to improve on the basis of the existing circuit, the existing circuit is divided into a plurality of areas, and design files containing sub-circuits in each area are sent to corresponding developers so that the developers can modify the circuit.
After the developer completes the circuit design work of the sub-circuit, the sub-circuit is sent to the circuit summarizing system in the form of first design files, and the circuit summarizing system judges whether each received first design file is an error file or not. Specifically, determining whether the first design file is an error file may be determining whether a suffix name of the first design file meets a preset condition; or judging whether the version information of the first design file meets the preset condition; or directly inputting the first design file into development software, judging whether a sub-circuit in the first design file in the development software can be combined with a local main circuit, and if the sub-circuit cannot be combined, indicating that the current first design file is an error file.
S11: if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information.
It should be noted that, the error file refers only to a design file based on an error version by a developer, and the condition of the circuit in the file is not limited. Therefore, in order to prevent the circuit in the error file from being abnormal, the sub-circuit information in the error file is integrated into the main circuit to cause circuit failure, and the sub-circuit in the error file needs to be detected. If the difference between the subcircuit in the error file and the subcircuit distributed to the design file of the developer by the circuit summarizing system is too large, deleting the error file; or sending an alarm to the manager to facilitate the manager to determine the sub-circuits in the error file.
In the implementation, when the file sent by any developer is detected to be an error file, the error file is analyzed to obtain the coordinate information of the sub-circuit and the sub-circuit element information in the error file. The coordinate information is the coordinate information of the current sub-circuit in the whole target circuit, and it is noted that a coordinate system needs to be established in the target circuit in advance to obtain the coordinate information of each point in the target circuit, and after the sub-circuit division work is completed, the coordinate information of the edge line segment of each sub-circuit is determined.
Further, the sub-circuit element information includes at least: the components included in the sub-circuits, the connection relationship between the components, the coordinate information of the circuit traces, and the like are not limited herein.
S12: and creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file.
In a specific implementation, an area in the main circuit file corresponding to the sub-circuit in the error file is determined according to the sub-circuit coordinate information, and a second design file of the circuit including the area is created. The second design file is a blank file only comprising the original sub-circuit, and the sub-circuit can be normally combined with the main circuit in the main circuit file because the version of the second design file is correct. And importing the information of the sub-circuit elements in the error file into a second design file, so that the purpose of merging the sub-circuit and the main circuit can be realized.
Further, when the sub-circuit element information is written into the second design file, all the sub-circuit element information may be written into the second design file, or only the sub-circuit element information that has changed or the element information designated by the manager may be written into the second design file, which is not limited herein.
S13: the second design file is incorporated into the master circuit file to obtain the target circuit.
It should be noted that during the circuit design process, there may be multiple error files, and when the sub-circuits in these files are missing, the circuit is incomplete, and does not meet the design requirements. Therefore, it is necessary to incorporate each second design file into the main circuit file to acquire the target circuit.
The embodiment provides a circuit design error processing method, which comprises the following steps: acquiring each first design file and judging whether each first design file is an error file or not; if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information; creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file to acquire the second design file; the second design file is incorporated into the master circuit file to obtain the target circuit. Therefore, in this embodiment, when it is detected that the first design file sent by the developer is an error file, element information and coordinate information of a sub-circuit in the error file are extracted, and these information are written into a second design file established based on the main circuit file, so as to prevent the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, resulting in waste of work of the developer. Thereby improving the circuit development efficiency.
In a specific implementation, before the step of obtaining each first design file, the method further includes: acquiring a circuit design requirement; dividing a target circuit into a main circuit and at least one target sub-circuit according to circuit design requirements; and sending each target sub-circuit to each developer to complete task allocation.
In the development process, a development manager divides an existing circuit into a plurality of areas according to circuit design requirements, and sends design files containing sub-circuits in each area to corresponding developers so that the developers can modify the circuit and arrange the circuit on a PCB.
As shown in fig. 1, the whole circuit is divided into four different regions, namely, part 1, part 2, part 3 and part 4. It should be noted that the boundary lines of different parts cannot overlap and cross each other to prevent the work of different developers from interfering with each other.
Further, to facilitate the division of the circuit, a coordinate system may be established in the circuit board to determine coordinate information of points in the circuit. The origin of the coordinate system may be any point in the circuit or outside the circuit, and is not limited herein, and the point at the lower left of the circuit is usually taken as the origin of the coordinate system. After the coordinate system is established, the coordinates at each boundary break point of each part are determined through the line segment consultation function of the development tool, and the coordinates of each part are respectively recorded in a data structure (such as an array, a queue and a table). Taking part 1 as an example, the coordinates of the folding points of the boundary line segments are list1= (A1 (xa 1, ya 1), B1 (xb 1, yb 1), C1 (xc 1, yc 1), D1 (xd 1, yd 1), E1 (xe 1, ye 1), F1 (xf 1, yf 1), G1 (xg 1, yg 1), H1 (xh 1, yh 1), I1 (xi 1, yi 1), J1 (xj 1, yj 1)); in the same way, the coordinates of the break points of the edge line segments of the other parts are recorded in other different data structures. It should be noted that the coordinates of the edge line segments of all the parts need to be recorded clockwise or anticlockwise in sequence, so that the positions of the parts can be determined according to the connection line in the clockwise or anticlockwise in other files.
As a preferred embodiment, determining whether an error file exists in each first design file includes: judging whether the first design file and the main circuit file can be combined or not; if the first design files cannot be combined, determining that the current first design files are error files.
Specifically, the first design file is read into the circuit development tool, and if the circuit development tool cannot identify the first design file, or if the circuit development file identifies a sub-circuit in the first design file but the sub-circuit cannot be connected with the main circuit board (cannot be connected or cannot work normally after being connected), the current first design file is an error file.
When there is an abnormality or error in the circuit in the error file, it may cause the sub-circuit information to be incorporated into the main circuit, resulting in the main circuit failure. To solve this problem, it is also necessary to detect sub-circuits in the error file. If the difference between the subcircuit in the error file and the subcircuit distributed to the design file of the developer by the circuit summarizing system is too large, deleting the error file; or sending an alarm to the manager to facilitate the manager to determine the sub-circuits in the error file.
On the basis of the above embodiment, before the step of creating the second design file according to the sub-circuit coordinate information, the method further includes:
judging whether the difference degree between a sub-circuit in the error file and a target sub-circuit is lower than a difference degree threshold value;
and if the difference degree is lower than the difference degree threshold value, executing the step of creating a second design file according to the sub-circuit coordinate information.
Further, the degree of difference includes a first degree of difference for characterizing differences in the manner of circuit connection and a second degree of difference for characterizing circuit elements.
In a specific implementation, when the amount of tasks completed by a developer in the task file with the wrong version is small, or when the tasks completed by the developer have errors due to the fact that the task file has errors, the sub-circuit information in the error file is meaningless to be introduced into the main circuit, and development efficiency is slow. To solve this problem, it is necessary to determine whether the degree of difference between the sub-circuit in the error file and the target sub-circuit is lower than a degree of difference threshold including a first degree of difference for characterizing the difference in circuit connection patterns and a second degree of difference for characterizing the circuit elements. When the difference degree between the sub-circuit in the error file and the target sub-circuit is smaller than the threshold value, the connection mode of the circuits in the two circuits, the used circuit components, the selection types of the components and the like are relatively close, the work of a developer has value, and the step of creating the second design file according to the coordinate information of the sub-circuit is executed.
Furthermore, the sub-circuits in the error file can be subjected to functional test to judge whether the sub-circuits can meet the circuit design requirement, if the sub-circuits can not meet the circuit design requirement, the fault of the current circuit is indicated, and the current circuit is not required to be combined with the main circuit.
In this embodiment, before the step of creating the second design file according to the sub-circuit coordinate information is performed, it is determined whether the difference between the sub-circuit in the error file and the target sub-circuit is lower than a difference threshold, so as to prevent the circuit in the error file from having abnormal or wireless data, and affect the circuit development efficiency.
As a preferred embodiment, creating the second design file from the sub-circuit coordinate information includes: determining a target sub-circuit of a region corresponding to the sub-circuit coordinate information in the main circuit file, and importing the target sub-circuit into the initial file; and initializing the initial file to obtain a second design file.
In specific implementation, after determining the error file, determining the part corresponding to the main file circuit and the error file according to the sub-circuit coordinate information in the error file, and exporting the part in a file form to be recorded as a new part. And performing an initialization operation on the file, deleting invalid information in the file, so that the subcircuit element information in the error file is written into the initial file to generate a second design file.
When the sub-circuit element information is written into the second design file, all the sub-circuit element information can be written into the second design file, or only the sub-circuit element information which is changed or the element information designated by the manager can be written into the second design file,
on the basis of the above embodiment, writing the sub-circuit element information into the second design file to obtain the second design file includes: determining difference elements of the sub-circuits in the error file and the target sub-circuit; the difference element is written into the second design file.
In this embodiment, the number of elements written in the second design file is reduced by determining the difference elements of the sub-circuit and the target sub-circuit in the error file and writing the difference elements in the second design file, so that the data writing efficiency is improved.
In the above embodiments, the circuit design error processing method is described in detail, and the present application further provides corresponding embodiments of the circuit design error processing apparatus. It should be noted that the present application describes an embodiment of the device portion from two angles, one based on the angle of the functional module and the other based on the angle of the hardware.
Fig. 3 is a block diagram of a circuit design error handling apparatus according to an embodiment of the present application, as shown in fig. 3, where the apparatus includes:
the judging module 10 is configured to obtain each first design file, and judge whether each first design file is an error file;
the analysis module 11 is configured to analyze the error file to obtain sub-circuit coordinate information and sub-circuit element information if the error file is an error file;
a first obtaining module 12, configured to create a second design file according to the sub-circuit coordinate information and the main circuit file, and write sub-circuit element information into the second design file;
a second obtaining module 13, configured to incorporate the second design file into the main circuit file to obtain the target circuit.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
In addition, the circuit design error processing device provided by the embodiment further comprises a task allocation module and a difference degree judging module.
The task allocation module is used for acquiring circuit design requirements; dividing the target circuit into a main circuit and at least one target sub-circuit according to the circuit design requirement; and sending each target sub-circuit to each developer to complete task allocation.
The difference judging module is used for judging whether the difference between the sub-circuit in the error file and the target sub-circuit is lower than a difference threshold; and if the difference degree is lower than the difference degree threshold value, executing the step of creating a second design file according to the sub-circuit coordinate information.
The present embodiment provides a circuit design error processing apparatus, including: acquiring each first design file and judging whether each first design file is an error file or not; if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information; creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file to acquire the second design file; the second design file is incorporated into the master circuit file to obtain the target circuit. Therefore, in this embodiment, when it is detected that the first design file sent by the developer is an error file, element information and coordinate information of a sub-circuit in the error file are extracted, and these information are written into a second design file established based on the main circuit file, so as to prevent the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, resulting in waste of work of the developer. Thereby improving the circuit development efficiency.
FIG. 4 is a block diagram of another circuit design error handling apparatus according to an embodiment of the present application, as shown in FIG. 4, the circuit design error handling apparatus includes: a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the circuit design error handling method according to the above embodiment when executing a computer program.
The terminal device for running the above circuit design error processing method provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in hardware in at least one of a digital signal processor (Digital Signal Processor, DSP), a Field programmable gate array (Field-Programmable Gate Array, FPGA), a programmable logic array (Programmable Logic Array, PLA). The processor 21 may also comprise a main processor, which is a processor for processing data in an awake state, also called central processor (Central Processing Unit, CPU), and a coprocessor; a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may be integrated with an image processor (Graphics Processing Unit, GPU) for taking care of rendering and rendering of the content that the display screen is required to display. In some embodiments, the processor 21 may also include an artificial intelligence (Artificial Intelligence, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, which, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the circuit design error handling method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. The operating system 202 may include Windows, unix, linux, among others. The data 203 may include, but is not limited to, the data related to the above-described circuit design manner, and the like.
In some embodiments, the circuit design error processing device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the configuration shown in fig. 4 is not limiting of the circuit design error handling apparatus and may include more or less components than those shown.
The circuit design error processing device provided by the embodiment of the application comprises a memory and a processor, wherein the processor can realize the following method when executing a program stored in the memory:
acquiring each first design file and judging whether each first design file is an error file or not;
if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information;
creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file;
the second design file is incorporated into the master circuit file to obtain the target circuit.
The present embodiment provides another circuit design error processing apparatus, including: acquiring each first design file and judging whether each first design file is an error file or not; if the information is an error file, analyzing the error file to obtain sub-circuit coordinate information and sub-circuit element information; creating a second design file according to the sub-circuit coordinate information and the main circuit file, and writing the sub-circuit element information into the second design file to acquire the second design file; the second design file is incorporated into the master circuit file to obtain the target circuit. Therefore, in this embodiment, when it is detected that the first design file sent by the developer is an error file, element information and coordinate information of a sub-circuit in the error file are extracted, and these information are written into a second design file established based on the main circuit file, so as to prevent the situation that the sub-circuit and the main circuit cannot be combined due to mismatching of the design file and the version of the main circuit file, resulting in waste of work of the developer. Thereby improving the circuit development efficiency.
Finally, the present application further provides an embodiment corresponding to the computer readable storage medium, where a computer program is stored, where the computer program when executed by a processor implements the steps described in the above method embodiments.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. With such understanding, the technical solution of the present application, or a part contributing to the prior art or all or part of the technical solution, may be embodied in the form of a software product stored in a storage medium, performing all or part of the steps of the method described in the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The method, the device and the medium for processing the circuit design errors are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it would be obvious to those skilled in the art that various improvements and modifications can be made to the present application without departing from the principles of the present application, and such improvements and modifications fall within the scope of the claims of the present application.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Claims (9)
1. A method for processing circuit design errors, comprising:
acquiring first design files, wherein the first design files are files which are sent to a circuit summarization system by a developer and comprise subcircuits designed by the developer; judging whether the first design files and the main circuit files can be combined or not so as to determine whether each first design file is an error file or not;
if the error file is the error file, analyzing the error file to acquire sub-circuit coordinate information and sub-circuit element information;
determining an error area corresponding to a sub-circuit in the error file in the main circuit file according to the sub-circuit information, creating a second design file of the circuit containing the error area, and writing the sub-circuit element information into the second design file; the second design file is a blank file only comprising an original sub-circuit, and the second design file is the same version of the main circuit file;
and the second design file is integrated into the main circuit file to obtain a target circuit, wherein the target circuit is a complete circuit corresponding to the circuit design requirement.
2. The circuit design error handling method of claim 1, wherein prior to the step of obtaining each first design file, further comprising:
acquiring the circuit design requirement;
dividing the target circuit into a main circuit and at least one target sub-circuit according to the circuit design requirement;
and sending each target sub-circuit to each developer to complete task allocation.
3. The circuit design error handling method of claim 2, wherein prior to the step of writing the sub-circuit element information into the second design file, further comprising:
judging whether the difference degree between a sub-circuit in the error file and the target sub-circuit is lower than a difference degree threshold value;
and if the difference degree is lower than the difference degree threshold value, executing the step of writing the sub-circuit element information into the second design file.
4. The circuit design error handling method of claim 1, wherein the writing the sub-circuit element information into the second design file comprises:
determining a target sub-circuit of a region corresponding to the sub-circuit coordinate information in the main circuit file, and importing the target sub-circuit into an initial file;
and initializing the initial file to obtain the second design file.
5. The circuit design error handling method of claim 3, wherein the degree of variance comprises a first degree of variance that characterizes differences in circuit connection patterns and a second degree of variance that characterizes circuit elements.
6. The circuit design error handling method of claim 2, wherein the writing the sub-circuit element information into the second design file comprises:
determining difference elements of a sub-circuit in the error file and the target sub-circuit;
and writing the difference element into the second design file.
7. A circuit design error handling apparatus, comprising:
the judging module is used for acquiring each first design file, wherein the first design files are files which are sent to a circuit summarizing system by a developer and comprise subcircuits designed by the developer; judging whether the first design files and the main circuit files can be combined or not so as to determine whether each first design file is an error file or not;
the analysis module is used for analyzing the error file to acquire sub-circuit coordinate information and sub-circuit element information if the error file is the error file;
the first acquisition module is used for determining an error area corresponding to a sub-circuit in the error file in the main circuit file according to the sub-circuit information, creating a second design file of the circuit containing the error area, and writing the sub-circuit element information into the second design file; the second design file is a blank file only comprising an original sub-circuit, and the second design file is the same version of the main circuit file;
and the second acquisition module is used for merging the second design file into the main circuit file to acquire a target circuit, wherein the target circuit is a complete circuit corresponding to the circuit design requirement.
8. A circuit design error handling apparatus comprising a memory for storing a computer program;
a processor for implementing the steps of the circuit design error handling method according to any one of claims 1 to 6 when executing said computer program.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when executed by a processor, implements the steps of the circuit design error handling method according to any one of claims 1 to 6.
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