JPS6191903A - Chip varister - Google Patents
Chip varisterInfo
- Publication number
- JPS6191903A JPS6191903A JP59213910A JP21391084A JPS6191903A JP S6191903 A JPS6191903 A JP S6191903A JP 59213910 A JP59213910 A JP 59213910A JP 21391084 A JP21391084 A JP 21391084A JP S6191903 A JPS6191903 A JP S6191903A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- chip
- varistor
- electrodes
- surge absorber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、家電製品及び制御装置の電子回路を雷サージ
等から保護するために利用されるチップバリスタに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a chip varistor used to protect electronic circuits of home appliances and control devices from lightning surges and the like.
従来例の構成とその問題点
半導体を使用した家電製品及び制御装置の電子回路は雷
サージ等が侵入してくると機器の破壊や誤動作などのト
ラブルが発生する。Conventional configurations and their problems When lightning surges or the like invade the electronic circuits of home appliances and control devices that use semiconductors, troubles such as equipment destruction and malfunctions occur.
そのため、第３図に示すように、電子機器（］）の前に
サージ吸収器（２）を挿入してサージから電子機器（１
）を保護している。サージ吸収器（２）は、線間と大地
間に接続されるもので、３つの外部端子を有する。Therefore, as shown in Figure 3, a surge absorber (2) is inserted in front of the electronic device () to protect it from surges.
) is protected. The surge absorber (2) is connected between the lines and the ground, and has three external terminals.
第４図は、従来のサージ吸収器を示し、（３）は電極、
（４） （５） （６）はバリスタ素子（以下素子とい
う）、 （７）はエポキシ樹脂、（８）は絶縁ケースで
、素子（５）が線間に接続され、素子（４）と素子（６
）が大地間に接続される。サージ吸収器（Ａ）は、各素
子（４） （５） （６）に３本の電極（３）をハンダ
付けしたものを絶縁ケース（８）に入れ、エポキシ樹脂
（７）でモールドして製造されるが、３ケの素子（４）
（５） （６）を同時にハンダ付けすることは非常に
難かしく、工程に時間がかかり、また部品点数が多いた
め、価格が高くなり形状も大きくなるという問題があっ
た・
発明の目的
本発明は上記従来の問題を解消するもので、製造工程が
簡単で、小形かつ安価なチップバリスタ（サージ吸収器
）を提供することを目的とする。Figure 4 shows a conventional surge absorber, where (3) is an electrode;
(4) (5) (6) is a varistor element (hereinafter referred to as the element), (7) is an epoxy resin, (8) is an insulating case, and the element (5) is connected between the wires, and the element (4) and the element (6
) is connected to the earth. The surge absorber (A) consists of three electrodes (3) soldered to each element (4), (5), and (6), placed in an insulating case (8), and molded with epoxy resin (7). Manufactured with 3 elements (4)
(5) It is very difficult to solder (6) at the same time, the process takes time, and there are many parts, so there are problems such as high price and large size.Purpose of the InventionThe present invention The object of the present invention is to solve the above-mentioned conventional problems, and to provide a chip varistor (surge absorber) that has a simple manufacturing process, is small, and is inexpensive.
発明の構成
上記ｉ的を達成するため、本発明は、バリスタ素子に、
その上面に互いに平行な２つの上部電極とその下面に前
記上部電極と直交するに互いに平行な２つの下部電極と
を設け、上部電極の一方の電極とこの上部電極に対向す
る下部電極の一方のｆｆ１１１とをバリスタ素子を貫通
して設けた穴に充填した電極材を介して電気的に接続し
た構成としたもので、雷サージ等が侵入した場合、互い
に対向している上部電極と下部電極のうち、バリスタ素
子に設けた穴に充填した電極材によって電気的ｌこ接続
されていない３ケ所でサージを吸収でき、小形化が可能
でかつ製造工程を非常に簡単にできるものである。Structure of the Invention In order to achieve the above-mentioned objective, the present invention provides a varistor element with the following features:
Two upper electrodes parallel to each other are provided on the upper surface thereof, and two lower electrodes parallel to each other are provided on the lower surface thereof, and one electrode of the upper electrode and one of the lower electrodes opposite to this upper electrode are provided. The FF111 is electrically connected to the varistor element through an electrode material filled in a hole made through the varistor element, so that in the event of a lightning surge, etc., the upper and lower electrodes facing each other will be connected to each other. Of these, surges can be absorbed at three locations that are not electrically connected by the electrode material filled in the holes provided in the varistor element, allowing miniaturization and greatly simplifying the manufacturing process.
実施例の説明
以下、本発明の一実施例を図面に基づいて説明する。第
３図と第４図は本発明に係るチップバリスタ（サージ吸
収器）を示し、第３図はチップバリスタ（Ｂ）の平面図
、第４図は第３図における■−■断面図である。（９）
は薄板状のバリスタ素子（以下素子という”） 、 （
１０）は上部電極で、素子（９）の上面に互いに平行に
２つ設けられている。 （１１）は素子（９）の下面に
設けた下部電極で、下部電極（１１）は互いに平行に２
つ設けられ、上部電極（１０）に直交している。（１２
）は穴で、この穴（１２）は上部電極（１０）と下部電
極（１１）が対向する部分の素子（９）を貫通して設け
ら九、穴（１２）に充填される電極材（１３）によって
対向する一組の上部電極（ｌＯ）と下部電極（１１）と
が電気的に接続される。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 3 and 4 show a chip varistor (surge absorber) according to the present invention, FIG. 3 is a plan view of the chip varistor (B), and FIG. 4 is a sectional view taken along the line ■-■ in FIG. 3. . (9)
is a thin plate-shaped varistor element (hereinafter referred to as "element"), (
10) are upper electrodes, two of which are provided parallel to each other on the upper surface of the element (9). (11) is a lower electrode provided on the lower surface of the element (9), and the lower electrodes (11) are arranged in parallel to each other.
The upper electrode (10) is perpendicular to the upper electrode (10). (12
) is a hole, and this hole (12) is provided through the element (9) in the part where the upper electrode (10) and the lower electrode (11) face each other. 13), a pair of opposing upper electrodes (lO) and lower electrodes (11) are electrically connected.
チップバリスタ（Ｂ）は、素子、（９）の上面の所定位
ｉｔこ上部電極（１０）を印刷脆燥後、下面の所定位置
に下部電極（１１）を印刷乾燥したものを数１００℃で
熱処理して焼付けることにより製造される。The chip varistor (B) is made by printing an upper electrode (10) at a predetermined position on the upper surface of the element (9) and brittle it, then printing a lower electrode (11) at a predetermined position on the lower surface and drying it at several hundred degrees Celsius. Manufactured by heat treatment and baking.
そのため、従来の製造方法と比較すると、難かしいハン
ダ付けやエポキシ樹脂（７）によるモールド等の行程が
なくなり、電極の印刷だけになり製造工程が簡単になり
、かつ、チップ状であるため小形化できる。Therefore, compared to conventional manufacturing methods, difficult steps such as soldering and molding with epoxy resin (7) are eliminated, and the manufacturing process is simplified as only the electrodes are printed.In addition, the manufacturing process is made smaller because it is in the form of a chip. can.
発明の詳細
な説明したように本発明によれば、バリスタ素子は、１
ケでよいため、小形化が可能であると共に、製造工程を
簡素化でき、かつ部品点数を減少できるので安価なチッ
プバリスタ（サージ吸収器）を提供できる。DETAILED DESCRIPTION OF THE INVENTION According to the present invention, the varistor element comprises 1
Since only one chip is required, it is possible to reduce the size, simplify the manufacturing process, and reduce the number of parts, making it possible to provide an inexpensive chip varistor (surge absorber).
第１図および第２図は本発明に係るチップバリスタの一
実施例を示し、第１図は平面図、第２図は第１図におけ
る１ｔ−ｕ断面図、第３図はサージ吸収器の使用状態図
、第４例は従来のサージ吸収器の正面断面図である。
（９）・・・バリスタ素子、（１０）・・・上部電極、
（ｌｌ）・−・下部電極、（１２）・・−穴、（１３）
・・・電極材代理人 森 本 義 弘
第１図
第２図1 and 2 show an embodiment of the chip varistor according to the present invention, FIG. 1 is a plan view, FIG. 2 is a sectional view taken along line 1tu in FIG. 1, and FIG. 3 is a surge absorber. The fourth example of the usage state diagram is a front sectional view of a conventional surge absorber. (9)... Varistor element, (10)... Upper electrode,
(ll)---lower electrode, (12)---hole, (13)
... Electrode material agent Yoshihiro Morimoto Figure 1 Figure 2
Claims (1)
部電極とその下面に前記上部電極と直交する互いに平行
な２つの下部電極とを設け、上部電極の一方の電極とこ
の上部電極に対向する下部電極の一方の電極とをバリス
タ素子を貫通して設けた穴に充填した電極材を介して電
気的に接続したチップバリスタ。1. The varistor element is provided with two upper electrodes parallel to each other on its upper surface and two lower electrodes parallel to each other that are orthogonal to the upper electrodes on its lower surface, and one electrode of the upper electrodes is opposed to this upper electrode. A chip varistor that is electrically connected to one electrode of a lower electrode through an electrode material filled in a hole provided through a varistor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213910A JPS6191903A (en) | 1984-10-11 | 1984-10-11 | Chip varister |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59213910A JPS6191903A (en) | 1984-10-11 | 1984-10-11 | Chip varister |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6191903A true JPS6191903A (en) | 1986-05-10 |
| JPH0577163B2 JPH0577163B2 (en) | 1993-10-26 |
Family
ID=16647052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59213910A Granted JPS6191903A (en) | 1984-10-11 | 1984-10-11 | Chip varister |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6191903A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4730117U (en) * | 1971-05-06 | 1972-12-05 | ||
| JPS59175704A (en) * | 1983-03-25 | 1984-10-04 | 富士電機株式会社 | Voltage nonlinear resistance porcelain |
-
1984
- 1984-10-11 JP JP59213910A patent/JPS6191903A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4730117U (en) * | 1971-05-06 | 1972-12-05 | ||
| JPS59175704A (en) * | 1983-03-25 | 1984-10-04 | 富士電機株式会社 | Voltage nonlinear resistance porcelain |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0577163B2 (en) | 1993-10-26 |
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