JPS6190343U - - Google Patents
Info
- Publication number
- JPS6190343U JPS6190343U JP1984174712U JP17471284U JPS6190343U JP S6190343 U JPS6190343 U JP S6190343U JP 1984174712 U JP1984174712 U JP 1984174712U JP 17471284 U JP17471284 U JP 17471284U JP S6190343 U JPS6190343 U JP S6190343U
- Authority
- JP
- Japan
- Prior art keywords
- logic
- binary signals
- receiving device
- voltage
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 230000002159 abnormal effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 1
Landscapes
- Monitoring And Testing Of Transmission In General (AREA)
Description
第１図はこの考案の一実施例を示すブロツク図
、第２図は第１図に示す装置の動作状態を示す図
、第３図は従来の受信装置の点検手段を示す図で
ある。
図において１は受信装置、２はスピーカ、３は
アンテナ、４は論理回路、５はスケルチ開閉信号
、６はＡＧＣ電圧、７はＲＦ入力検波電圧、８は
表示器である。なお、各図中同一符号は同一部分
を示す。
FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing the operating state of the device shown in FIG. 1, and FIG. 3 is a diagram showing inspection means of a conventional receiving device. In the figure, 1 is a receiving device, 2 is a speaker, 3 is an antenna, 4 is a logic circuit, 5 is a squelch opening/closing signal, 6 is an AGC voltage, 7 is an RF input detection voltage, and 8 is a display. Note that the same reference numerals in each figure indicate the same parts.
Claims (1)
圧とＲＦ入力検波電圧とを検出する手段と、この
検出した各電圧を論理Ｈ、論理Ｌの２値信号に変
換する手段と、この変換された２値信号を入力し
、入力した２値信号の論理の組合せに従つて上記
受信装置の動作状態が正常であるか異常であるか
を示す信号を出力する論略回路と、この論理回路
の出力を表示する表示器とを備えた受信機能点検
回路。 means for detecting the AGC voltage, squelch switching signal voltage, and RF input detection voltage from the receiving device; means for converting each of the detected voltages into binary signals of logic H and logic L; and the converted binary signals. a logic circuit that outputs a signal indicating whether the operating state of the receiving device is normal or abnormal according to the logic combination of the input binary signals, and displays the output of this logic circuit. Receiving function check circuit equipped with a display.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984174712U JPH0233415Y2 (en) | 1984-11-16 | 1984-11-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1984174712U JPH0233415Y2 (en) | 1984-11-16 | 1984-11-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6190343U true JPS6190343U (en) | 1986-06-12 |
| JPH0233415Y2 JPH0233415Y2 (en) | 1990-09-07 |
Family
ID=30732327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1984174712U Expired JPH0233415Y2 (en) | 1984-11-16 | 1984-11-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0233415Y2 (en) |
-
1984
- 1984-11-16 JP JP1984174712U patent/JPH0233415Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0233415Y2 (en) | 1990-09-07 |
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