JPS6188333A - Binary operation circuit - Google Patents

Abstract

PURPOSE:To improve the performance by providing an FF by-pass function to a binary pipeline operating device split into plural pipeline stages and using a preceding operation and a succeeding operation to reduce the instruction execution time when referenced registers are competed. CONSTITUTION:An exponential subtractor 20 compares exponential parts of operands 1, 2 to detect a digit matching bit number. A manissa having a smaller exponential part is shifted by a shifter 22 while being matched for output's share of the subtractor 20. Then an adder 24 of the mantissa applies carry transmission addition in 64 bits and the shifter 26 applies binary normalizing to the result of addition. Stage registers 21, 23, 25, 27 set respectively outputs of pipeline stage operation circuits 20, 22, 24, 26, the registers release the holding function of an FF 10 and gives the input of the output side as it is. Thus, the instruction execution time when referenced registers are competed by using the preceding and succeeding operations.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to binary arithmetic control, and particularly to a pipeline arithmetic control system.

Conventional technology: Conventionally, in this type of binary arithmetic circuit, various operations X (for example, addition, multiplication, shift, logical operation, division, etc.) between binary floating point data or fixed point data are performed in a pipeline manner. It is provided in the processing device and consists of an arithmetic register that stores the operated operand, an output crossbar that reads the operand data from the arithmetic register, and various binary pipeline arithmetic units (for example, floating/fixed a circuit for connecting the output of the output crossbar to the input of each binary arithmetic unit, It consists of an input crossbar that inputs to the calculation register, and executes and controls the calculation processing in a pipeline manner, but the calculation is divided into functional units of multiple stages, and circuits such as flip-flops or latches are installed between each pipeline stage. Since there are registers created in Without this, the instruction execution time would increase, which would be a factor in reducing system performance.

Purpose of the Invention The present invention has been made in view of the above-mentioned conventional circumstances.
Therefore, an object of the present invention is to provide a binary arithmetic unit in a binary arithmetic circuit, a multi-stage pipeline arithmetic stage circuit, a stage register for storing the output of the circuit, and a register that releases the holding function of the stage register. The above-mentioned drawbacks are solved and the operation processing time is shortened in cases where there is a conflict between the registers referenced by the preceding operation and the subsequent operation. The object of the present invention is to provide a new binary arithmetic circuit that can improve system performance.

Structure of the Invention In order to achieve the above object, a binary arithmetic circuit according to the present invention includes an arithmetic register that stores a binary operand, and a gate from the arithmetic register in a binary arithmetic circuit that processes binary data. An output crossbar that reads out and selects the π operand, a group of binary arithmetic units that executes various operations, and a group of binary arithmetic units that is divided into a plurality of stages, each of which has a pipeline arithmetic stage circuit and the pipeline. It consists of a stage register that stores the output of the stage circuit, and a register holding function canceling means that cancels the holding function of the stage register and propagates the input to the register to its 11 outputs, and the output of the output crossbar is connected to the binary arithmetic unit. an input crossbar that inputs the output of the binary arithmetic unit group and supplies it to the arithmetic register, and an execution mode specifying flip-flop that can be set and reset from the outside, and the execution mode The present invention is characterized in that the output of the designated flip-flop is used to identify and control whether the binary arithmetic unit group is to be executed by bip-line processing or by instruction-level sequential processing by the register holding function canceling means.

Embodiments of the Invention Next, seven preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In FIG. 1, reference number 1 is the input crossbar, which is 8 bytes (6-bits) wide. 2 is a calculation register,
It contains eight 8-byte registers and is a storage register for floating point data. Reference numeral 3 denotes an 8-byte wide output crossbar, which is a circuit for selecting an operand from the operation register 2. 4 is a binary floating point adder, which is a circuit that inputs two operands, which are 8-byte floating-point data, executes addition processing, and obtains an 8-byte result.

5 is a binary floating point multiplier, which is a circuit which executes multiplication processing by inputting two operands, which are 8 bytes of floating point data, to obtain an 8 byte result. 6 is a binary floating-point divider, which is a circuit that obtains 8-byte data as a division result from two floating-point operands. 7 is a binary number nok, which is a circuit that executes a left/right shift of an 8-byte operand. 8 is a logic operation unit, which is a circuit that executes logic operations between 8-byte logic data.

The outputs of the respective arithmetic units indicated by reference number 4.5.6.7.8K are connected to the input crossbar 1. Reference numeral 9 denotes an execution mode designation flip 70 knob 1 for identifying and controlling whether to execute execution of the binary arithmetic unit group in a pipeline manner or to execute sequential processing at the instruction level using the register holding function canceling means.
This is a circuit that sets and resets 0 from the outside.

FIG. 2 is a detailed i11 circuit diagram of the floating point adder 4 of FIG. The floating point data format which is the input operand to this adder 4 is as shown in FIG. In the figure, reference symbol SM is the sign bit of the mantissa, E is the exponent, and M
indicate the mantissa part, respectively.

In FIG. 2, the reference number nod is an exponent subtracter that compares the exponent parts of operand 1 and operand 20 to detect the number of digit alignment bits. n is operand 1.2, and the mantissa part with the smaller exponent part is shifted by the output of exponent subtraction 6 addition to digit adjustment chic. Sae is a mantissa adder and is a 64-bit wide carry propagation adder. 26 is a shifter for binary normalizing the addition result. 21, 23, 25
．． 27 is a stage register for setting the output of each pipeline stage arithmetic circuit 20, 22, 24, and 26, respectively.

These registers have the function of canceling the holding function of the flip-flop and propagating the input as is to the output.

Next, we will explain the aspect of pipeline operation for floating-point addition in the fourth section.
This will be explained with reference to the time chart shown in the figure.

This example is a case where two consecutive floating point number 1i instructions occur, and as shown in S3←S1+82 (51 to S6 are operation S6←S4 + Ss registers), there is a conflict between the operation registers referenced between the instructions. This is a case where there is no

In the machine cycle T1, the calculation register 81. The S2 signal is read out through the output crossbar 3. T2, Ts.

In cycles T4 and Ts-1/-, the pipeline stage processes of exponent comparison 6 addition, digit alignment shifter n, mantissa adder, and normalization thick are executed, respectively. T61t
It passes through the input crossbar 1 in cycles and is stored in the calculation register S3 in cycles T7. Subsequent instruction S6←S4+ 3
Processing No. 5 is also processed in a pipeline manner with a delay after IT of the preceding instruction.

Next, if two floating-point addition instructions occur in succession, and there is a conflict between the operation registers referenced between the two operations, for example, in the case of S3←S1+82 (81 to S5 are operation S5←85+84 registers). A time chart for a conventional circuit is shown in FIG. T1-T7
The operation of the cycle is the same as in FIG. In FIG. 4, the subsequent operation is started from the T2 cycle, but in FIG. 5, it is started after the preceding operation is completed, that is, from the T8 cycle. This is because the contents of the register stored in the preceding operation are used as operands in the subsequent operation. In this way, the 4 between the operation registers referenced in the preceding operation and the subsequent operation is
If there is a match, the operations are processed serially and the piper
If the stage cycle time of f is long, then the performance/::1. j
It became a factor that decreased productivity.

The present invention focuses on the above points, and by providing a holding function release means in the stage register provided for each pipeline stage, the present invention provides synchronization control (such as clock skew flip-flop set-up time). (The calculation processing time is 7:'1L9, which is 67
+.

S3←S1 + 32S5←S in this implementation sequence in Figure 6
A time chart for the case of 3+34 is shown. Addition processing of exponent comparison, digit alignment shift, anti-two part addition, and normalization shift is 3
The embroidery ends in one cycle, and the embroidery is shortened by one cycle compared to conventional methods.

As explained above, by providing 7 lip-flop bypasses in the binary piper 1/j member γ unit divided into 3 pipeline stages,
The present invention provides a device that reduces instruction execution time and improves system performance when there is contention between registers referenced by preceding and subsequent operations.

Effects of the Invention As explained above, the present invention has flip-flop holding function canceling means in the binary pipeline stages 1 and 5 divided into a plurality of pipeline stages, and performs the preceding operation and the subsequent operation. This has the effect of shortening instruction execution time and improving system performance when there is contention between registers referenced by .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a detailed block diagram of the binary adder 4 shown in Figure 1, Figure 3 is a diagram showing the floating point data format that is input to the binary adder 4, and Figure 5 is a prior art circuit. 4 and 6 are time charts of this embodiment. 1...Input crossbar, 2...Arithmetic register, 3...
・Output crossbar, 4...binary adder, 5...binary multiplier, 6...binary divider, 7...binary shifter, 8...
...Logic operator, 9...Flip-flop set circuit, 10...Flip 70 tube, addition...Exponent comparator,
n...digit matching chic, sae...mantissa adder,...
...Normalized chic, 21°, 25.27...Register patent Applicant: NEC Corporation Representative, Patent attorney Yutabe Kumagai Figure 1 1°C Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In a binary arithmetic circuit that processes binary data, there are arithmetic registers that store binary operands, output crossbars that read and select operands to be operated on from the arithmetic registers, and binary arithmetic units that perform various operations. Then, the binary arithmetic unit includes each pipeline arithmetic stage circuit divided into a plurality of stages, a stage register for storing the output of the pipeline stage circuit, and a holding function of the stage register, and input to the register. a circuit for connecting the output of the output crossbar to the group of binary arithmetic units; and an input crossbar for inputting the output of the group of binary arithmetic units and supplying the output to the arithmetic register. and an execution mode specifying flip-flop that can be set and reset from the outside, and the output of the execution mode specifying flip-flop causes the binary arithmetic unit group to be executed by pipeline processing, or the register holding function cancellation means executes the instruction. A binary arithmetic circuit characterized in that it discriminately controls whether to perform level sequential processing.