JPS6188161A - Speed signal detector - Google Patents

Abstract

PURPOSE:To remove the ripple of a detected speed signal almost completely and to improve response by detecting a DC voltage changing its polarity in accordance with the turning direction and proportional to the turning speed from the output of a two-phase type rotary encoder. CONSTITUTION:The 1st logical circuit 14 inputs two-phase pulse waves Ao, Bo having phase difference of 90<o> electric angle which are outputted from the two-phase type rotary encoder to control the 1st integrating circuit 2 and its output is turned to a pulse wave G through the 1st sample holding circuit 3, the 2nd integrating circuit 4, and a comparator 5. When receiving an output from a rotational direction deciding circuit inputting said two-phase pulse waves Ao, Bo, the 2nd logical circuit 4 controls the 3rd integrating circuit to actuate the 2nd sample holding circuit and the 4th integrating circuit. Consequently, a speed signal proportional to the rotational direction and having polarity corresponding to the rotational direction.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a speed signal detection device used as a speed sensor for a power source that requires speed control, such as a machine tool or a robot.

(Conventional configuration and its problems) Generally, in a servo system that performs mechanical control such as in an industrial robot, a speed loop is necessary to stabilize the operation of the servo system and improve responsiveness. . Therefore, in the past, a DC tacho generator was installed as a speed signal detector to detect the speed signal6, but since the DC tacho generator has rectifying brushes, maintenance and inspection were required and the handling was complicated. Furthermore, in a servo system that performs positioning control, it is necessary to also install a rotary encoder for detecting position signals.

It was becoming expensive.

Other conventional speed signal detection devices obtain speed signals by F/V converting the pulse output of a rotary encoder for detecting position signals, but in this case, responsiveness is If it is increased, the ripple at low speed becomes large, and when the ripple at low speed is smoothed and reduced, the response becomes poor.

(Object of the invention) The present invention has been made in view of the drawbacks of the conventional example, and
It is an object of the present invention to provide a speed signal detection device that has almost no ripples in a detected speed signal, has good responsiveness, and is inexpensive.

(Structure of the Invention) In order to achieve this object, the present invention provides a first logic circuit which receives as input two-phase pulse waves output from a two-phase rotary encoder and having a phase difference of 90 degrees electrical angle. and a first integrating circuit that includes an analog switch whose opening and closing are controlled by the output of the first logic circuit and integrates a constant current every 174 cycles of the two-phase pulse wave and outputs a DC voltage proportional to the cycle; a first sampling-and-hold circuit that receives the output of the first integration circuit; a second integration circuit that outputs a constant-period sawtooth wave with a slope proportional to the output of the first sampling-and-hold circuit; A comparator that compares the output of the integrating circuit with a predetermined value and converts it into a pulse wave, a rotation direction discrimination circuit that receives the two-phase pulse wave as input, and an output of the comparator and an output of the rotation direction discrimination circuit. a second logic circuit as an input; a third integration circuit that includes an analog switch whose opening and closing are controlled by the output of the second logic circuit and generates a voltage proportional to the pulse width of the comparator; and a third integration circuit. a second sampling and holding circuit whose input is the output of the circuit;
From the output of the two-phase rotary encoder, a DC voltage whose polarity varies depending on the direction of one rotation and which is proportional to the rotational speed is detected.

(Description of Embodiments) An embodiment of the present invention will be described in detail below with reference to FIGS. 1 to 5 of the drawings. In FIG. 1, la and lb are input terminals to which the output of the two-phase rotary encoder is respectively supplied, 2 is the first integrating circuit, 3 is the first sampling hold circuit, 4 is the second integrating circuit, 5 is a comparator, 6 is an exclusive OR circuit, 7 is an inversion circuit, 8, 9.10 and 11 are one-shot multi circuits, 12.13 is a NAND circuit, 14 is a first logic circuit, 15 is a clock circuit, 16
is an inverting circuit.

In FIG. 2, 18 is an AND circuit; in FIG. 3,
19 is a rotation direction discrimination circuit, 22 is a third integrating circuit, 23
24 and 25 are inversion circuits, 26 are one-shot multi-circuits, 27 are second logic circuits, and in FIG. 4, 20 are three-chip ICs,
21 is a fourth integrating circuit. Also, the positive power supply voltage is 10E
, the negative power supply voltage is -E.

Next, the operation of this embodiment will be explained in FIG. 4, which shows the waveforms of each part.
This will be explained with reference to FIG. Pulse waves of a two-phase rotary encoder having a phase difference of 90' electrical angle are supplied to input terminals 1a and 1b.
input 80 and B respectively. shall be. This input A in the first logic circuit 14. and B. The output of the exclusive OR circuit 6 whose input is C0, and co is the inverting circuit 7.
I turn around and get drunk. The outputs of the one-shot multi-circuits 8 and 9 having inputs co and G, respectively, are Q□ and C3 with a pulse width T□. Note that the pulse width T1 is T□< with respect to the minimum value ToMIN of the period T0 of the input A0.
T, IIIN/4. Next, one-shot multi-circuit 1 with Q□ and C3 as inputs, respectively.
The outputs of 0 and 11 are C2 and C4 of pulse width T2. Note that the pulse width T2 is T□ and T. For □8, T1<T2<T. Set it to be Mll/4.

Next, the output of the NAND circuit 12 whose input is the inverted signal Q2-Σ-C8 of the output Q2 is set as C□, the output of the NAND circuit 13 whose input is the inverted signal of C4 and ζ is set as 02, and the outputs Q1 and C3 Let the inverted signals of 2 and 2 be respectively cho and hai. Analog switch 511s21s3154 +SS
, S6. S and S are respectively C1, C2, C□,
Intoxication, Hi: Turns on when QJQ4TC2 and G are low.

Next, in the first integrating circuit 2, while the output C9 is low, the analog switches S0 and S2 are on and 83 is off, and the output D of the first integrating circuit 1 is
□ rises to Vi (1). Also, during T2 after the output C6 falls from high to low, in the first integrating circuit 2, the analog switch S5. SG and S7 are off, and output D2 is the output voltage V. (1) is retained. Next, analog switches SG and S7 are turned on, and the output D2 of the first integrating circuit 2 is set to 0■. Next, during T2 after the output C8 rises from low to high, the analog switches S2 and S3 are off in the first integrating circuit 2, and the output D
The engineer holds ■, (1). Next, analog switch S
2 and S are turned on, and the output D of the first integrating circuit 2
Set the engineering to 0■. Further, while the output C0 is high, the analog switches S and S6 are on and the switch 87 is off, and the output D2 of the first integrating circuit 2 is ν due to constant current integration. (2
). Hereinafter, similarly, the output D1 of the first integrating circuit 2
and the holding voltage of D2 is v, (2) , v, (2)
, v, (3) , Vl (3), and the output Co changes to the first integrator circuit 2 every cycle when the output Co is low.
It is converted into a DC voltage by the output D□, and the high period is 1
It is converted into a DC voltage by the output D2 of the first integrating circuit 2 every cycle.

Then by analog switches S4 and Ss.

The voltages held at the outputs D1 and D2 are input to the sampling and holding circuit 3 during T1 after being held. The sampling hold circuit 3 holds the previous input voltage while S4 and S8 are off. Let E be the output of the sampling hold circuit 3. In the second integrator circuit that receives the signal E as an input, the analog switch S , turns on when Baba is low, and generates a sawtooth wave F with a constant period T3, with a slope proportional to the input voltage E.

In the comparator 5 which receives the sawtooth wave F and the negative predetermined value V as input, when F≧V, the output G is set to high, and the pulse width of G is set to Tg. If T4 is negligible compared to T3, then T
, is inversely proportional to E3 and proportional to the rotation speed. If T4 is too large to be ignored as compared to T, as shown in Fig. 2, by using an AND circuit 18 that receives G and a tile as inputs, the pulse width T6 of the output H of the AND circuit 18 is reversed to E3. It is proportional to the rotation speed.

Next, a rotation direction discrimination circuit 19 that receives a two-phase pulse wave as input.
The output J outputs a positive voltage in the case of CCW rotation, and a negative voltage in the case of CCW rotation. In the second logic circuit 27 which takes J and G or H as input, J is input, and a limit circuit of a diode d and a resistor r converts the low voltage into a pulse P with Ov, and an inverting circuit 24 converts the low voltage into a pulse P of Ov. The signal is converted and inverted by an inverting circuit 25 using G or H as an input, and output is R. A one-shot multi-circuit 26 having R as an input outputs an output with a low pulse width T7 and a period T3. Analog switch S engineering. , S, 11812 and Sij are Ding, P, R, respectively.

Turns on when [ is low.

In the third integration circuit 22, when the rotation direction is ccv, Sl. and 512 are on, and during T5 when G is high or T when H is high, integration is performed with a constant current, and the output M is V3.
(0). Next is analog switch S engineering. , s1□,
S engineering 2゜513 are all off, T, -T, or T3-
M maintains V3(O) during Ts-T4. V3(0)
While holding V, (
0) is retained. Next, the analog switch S, is turned on and the integral value V, (O) is discharged. One after another, convert the pulse width T5 or TG into a voltage, V3 (1) lV
3 (2) ,... group. Here, the pulse period T of the clock can be set independently of the period of the pulse wave of the input rotary encoder, the period may be made small to improve responsiveness, or the necessary response frequency can be set to make signal processing easier. The frequency may be set to about 10 times higher. T, or T6. The value when is the maximum rotation speed is T5, +TGMA
If X, TST4AXTTGKAI<T3-T'
Set each value to satisfy r-T4. When the rotation direction is CW, the analog switch S is on and SXO is off, so the sign of the output voltage M is reversed, but the other functions are the same. The output N of the sampling and holding circuit 23 obtained in this manner is a speed signal that is proportional to the rotational speed and has a polarity that differs depending on the rotational direction.

Further, as shown in FIG. 4, the sign of the output pulse differs depending on the rotation direction, and the pulse width outputs a pulse wave K proportional to the rotational speed, and the output is obtained by smoothing it by an integrating circuit 21 which receives K as an input. The average value of L is proportional to the rotation speed.

A circuit corresponding to a conventional F/V circuit can also be easily constructed.

(Effects of the Invention) As described above, according to the present invention, when the pulse output of a two-phase rotary encoder is input, a DC voltage whose polarity differs depending on the direction of rotation, is proportional to the rotation speed, and has no ripples is generated with good response. In addition, it has excellent effects such as eliminating the need for a DC tacho generator in the servo system used for positioning control, eliminating the need for maintenance and inspection, and reducing costs.

[Brief explanation of drawings]

1 to 3 are block diagrams of a speed signal detection device in one embodiment of the present invention, and FIG. 4 is a block diagram of a portion of a speed signal detection device in another embodiment of the present invention.
FIGS. 5 and 6 are timing waveform diagrams showing output waveforms of each part in FIGS. 1 to 4. FIG. la, lb-input terminal, 2, 4, 21.22-・
・Integrator circuit, 3, 23... Sampling hold circuit, 14.27... Logic circuit, 19... Rotation direction discrimination circuit, 20... Three-state IC, S1 to S engineering,
・Analog switch. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 4 A1 Figure 5 (a) CCWd private r-

Claims (2)

[Claims] (1) A first logic circuit that receives as input two-phase pulse waves output from a two-phase rotary encoder and having a phase difference of 90 degrees electrically; a first integrating circuit that integrates a constant current every 1/4 period of the two-phase pulse wave and outputs a DC voltage proportional to the period; and an output of the first integrating circuit is input. a first sampling and holding circuit that outputs a constant-period sawtooth wave with a slope proportional to the output of the first sampling and holding circuit; a comparator that compares and outputs a pulse wave corresponding to the magnitude relationship; a rotation direction discrimination circuit that receives the two-phase pulse waves as input; and an output of the comparator and an output of the rotation direction discrimination circuit. a second logic circuit as an input; a third integration circuit that includes an analog switch whose opening and closing are controlled by the output of the second logic circuit and generates a voltage proportional to the pulse width of the output of the comparator; a second sampling and holding circuit that receives the output of the third integrating circuit as an input; and extracting a speed signal proportional to the rotational speed and having a polarity corresponding to the rotational direction from the second sampling and holding circuit. Characteristic speed signal detection device. (2) A first logic circuit that receives as input two-phase pulse waves output from a two-phase rotary encoder and having a phase difference of 90 degrees electrically; a first integrating circuit that integrates a constant current every 1/4 period of the two-phase pulse wave and outputs a DC voltage proportional to the period; and an output of the first integrating circuit is input. a first sampling and holding circuit that outputs a constant-period sawtooth wave with a slope proportional to the output of the first sampling and holding circuit; a comparator that compares and outputs a pulse wave corresponding to the magnitude relationship; a rotation direction discrimination circuit that receives the two-phase pulse waves as input; and an output of the comparator and an output of the rotation direction discrimination circuit. a three-state IC that inputs the pulse and inverts the sign of the pulse depending on the rotation direction; and a fourth integrating circuit that receives the output of the three-state IC as an input; A speed signal detection device characterized in that it extracts a speed signal with a polarity corresponding to the direction of rotation.