JPS6186845A - Bus parity check circuit - Google Patents

Abstract

PURPOSE:To attain the mixed use of a circuit having a check circuit for bus parity and a circuit having no check circuit on a bus, by judging the propriety for execution of parity according to the presence or absence of a parity check enable signal. CONSTITUTION:When a read access is given to a parity presence slave 3 via a parity presence master 1, the lave 3 knows by an address signal on an address bus 5 that the slave 3 itself is selected. Thus the slave 3 delivers data to a data bus 6 and a data parity to a parity line 10 respectively. In this case, a signal PCENL is also delivered from a PCENL line 51 via a PCENL producing circuit 52a. The master 1 performs a parity check by the data and parity, and a parity generator checker 14a checks whether the data is normal or not. The checker 14a latches an abnormal signal if delivered. Then, whether the detection of faults is needed or not is judged by the signal PCENL.

Description

[Detailed description of the invention] [Industrial application field] Master this invention! 'fC4': This relates to a bus parity check circuit in which a parity check enable function is added to the r slave circuit.

[Conventional technology]

For example, in Figure 2, there is a document “Computer Design Technology [I] J
(CQ Publishing Co., Ltd., published February 15, 1970, 20
Adopts the parity generator e check circuit (for 8 bits, Fig. 5, 43) described on pages 0 to 203),
A bus parity check circuit is shown when a master without parity, a master without parity, a slave with parity, and a slave without parity are connected to one bus. In the figure, 1 is a master with no parity, 2 is a master with no parity, 3 is a parity re-slave, and 4 is a slave with no parity. '! y
t, 5 to 10 form a common bus A, where 5 is an address bus, 6 is a data bus, 7 is a read command line, and 8 is a write command line.

9 is the ACK line, 10 is the parity line, and 11a.

11b is an address generation circuit, 12a and 12b are data generation circuits, 13a and 13b are command generation circuits,
14a, 14b [parity generator/checker (hereinafter referred to as PG/C), 15a, 15b address matching circuit, 16g, 16bi memory or u engineering 10 circuits,
17a, 17b HACK circuit, 18a.

18bHD-FIIF, 19a to 19dH time delay circuit, 20a to 20 diAND circuit, 21a
.

21 bnOR circuit, 22 a, 22 bn P
This is a switching circuit for switching between using the G/C as a generator or as a checker.

The conventional bus parity check circuit is configured as described above, and when the parity page master 1 performs a 3ft read access to the slave with parity, the address is transmitted from the address generation circuit 11a of the parity master 1, and the data is transmitted from the tx data generation circuit 12a of the parity master 1. fta command generation time lol! 113
5. Address bus for each read command from a. The data bus 6, 'J-)'' is output to the command line 7. Then, the parity slave 2 learns from the address signal on the address bus 5 that it has been selected by the address matching circuit 15a, and the memory circuit 16a chip enable CE, address AD, IJ-)" gives a predetermined signal to the command generation circuit, outputs data to the data bus 6 and data parity to the parity line, and also serves as a chip enable that has the meaning of board selection. Since it takes time for the data to appear on the data bus, the time is extended by the time delay circuit 19b, and then the ACK signal is output to the ACK line 9 via the ACK circuit 17a. do. Here, a parity check is performed on the parity master 1 using the data on the data bus 6 and the parity on the parity line 10, and the PG/C
Check with 14a and apply the trigger with AND20a of the ACK signal and read command and the 7'c time delay 19a of data establishment, and if the abnormal signal is output from PG/c14a at the time of this triggering, then D. -F-F
'18a latches son and performs error processing.

Similarly, when a parity-less slave 4 is accessed for read, there is no parity bit, and the PG/C 14a of the parity page master 1 is checked.

Since the parity line 10 is idle, it may be determined that there is an abnormality depending on the data.

In addition, in the case of write access, the address is sent from the address generation circuit 11 & of the parity master 1 to the data generation circuit W.
Data is output from I112a, and a write command is output from command generation circuit 13a to address bus 5, data bus 6, and write command line 8, respectively. At this time, the PG/C 14a is used as a parity cinerator by switching with a write command, and outputs odd and even parity bits to the parity line 10. When the parity bit is input by slave 3 with parity,
Similar to the parity arm master 1, the PG/c 14b performs a parity check based on data and parity, and if an error occurs, performs error processing. - Katana Balitei no slave 4
When you access the light.

Since this non-parity slave 4 does not have a parity check function, a parity error will not occur even if there is no parity.

In other words, when the master 2 without parity performs read access to the slave 3 with parity, the address generation circuit 1ib outputs an address, the data generation circuit 12b outputs data, and the command generation circuit 13b outputs a read command. Master 1 with parity in 3
Performs the same processing as data read from . However, since the non-parity master 2 does not have a parity check function, only data is read without causing a parity error. Therefore, when reading the parity-less slave 4, only data is read. '? In the case of a 7t write access, only the data of the master 2 without parity is input to the slave 3 with parity, and since a parity check is performed, it may be determined that the data is abnormal. Furthermore, parity-less slave 4
Even if there is no parity in a write access, even if there is no parity check function, a parity error will not occur.

[Problem that the invention seeks to solve]

What is the parity mask in the conventional bus parity check circuit like the one above? Since a slave with 7cU parity forcibly performs a parity check, there are problems such as it is not possible to perform a parity check in some cases and not to perform a parity check in other cases.

The present invention was made to solve these problems, and since it is determined whether or not parity can be executed based on the presence or absence of a varicheck enable signal, a circuit that has a circuit that checks pass parity and a circuit that does not have a pass parity check circuit can be passed. The object of the present invention is to obtain a bus parity check circuit that can be used in combination with the above.

[Means for solving problems]

The bus parity check circuit according to the present invention includes a master with parity and a slave with parity, each having a parity-equipped non-pulling generation circuit that outputs a parity check enable signal, and a master without parity and a slave without parity, which does not have the generation circuit. This is a configuration in which parity-less slaves are mixed on a common bus.

[Effect]

In this invention, it is possible to determine whether or not a parity check can be executed based on the presence or absence of the parity check enable signal, so even if a circuit that has a path parity check circuit and a circuit that does not have a path parity check circuit coexist, there will be an error in parity check abnormality detection. Detection can be prevented.

〔Example〕

FIG. 1 shows a bus parity check circuit according to an exemplary embodiment of the present invention, in which 5 i, 52a, S2b+5 are shown.
Except for 3a and 53b, the same reference numerals as in FIG. 2 indicate the same or equivalent parts as in the conventional device described above. In the figure, 51
PCENL signal (parity check enable signal)
Lines, 52a, 52b UPCENL (parity check enable) generation circuit, 53a, 53b [3 manual AN
This is the D circuit.

In the f'L7j bus parity check circuit configured as described above, when the master 1 with parity performs read access to the slave 3 with parity, the address is transferred from the address generation circuit 11a of the master 1 with parity to the data generation circuit 12a of the case data generation circuit 12a. Data and a read command are output from the command generation circuit 13a to the address bus 5, data bus 6, and read command line 7, respectively.

Then, the retained slave 3 learns from the address signal on the address bus 5 that it has been selected by the address %15a, and sends the chip enable CE, address AD, and read command line to the memory circuit 16a. In order to provide the necessary signals, output the data to the data bus 6, and output the data parity to the retail line 10, wait for the meaning of board selection. Since it takes time for the data to appear on the ACK circuit, the time delay circuit 19b extends the time by that time, and then the ACK signal is sent to the A via the ACK circuit 17a.
Output to CK line 9.

At this time, the PCENL signal (parity check enable signal) indicating that a parity check is required is also sent to the PCENL line 5.
1 through the PCENL generation circuit 52a. Here, the master 1 with parity performs a parity check using the data on the data bus 6F and the parity on the parity line 10, checks whether the data is normal using the PG/c 14a, and sends an ACK signal, read command, and PCE.
A trigger is applied by the AND 53b of the NL signal and the time delay 19a for data establishment, and at the time the trigger is applied, an abnormal signal is output from the PG/c 14a and the signal is latched. At this time, since the PCENL signal is output from master 1 with parity, this signal is used to determine whether or not abnormality detection is necessary.Here, when reading access to slave 4 without parity, the parity bit is Since there is no parity, P of master 1 with parity
Parity line 10 when checking in G/C14a
has become idle, and depending on the data, it may be determined to be abnormal.

Historically, in the case of write access, the address is received from the address generation circuit 11a of the master with parity 1, the data is received from the data generation circuit 12a, and the command generation t7. Times Wit 1
3 Write command from a to PCENL, generation circuit 5
The PCENL signal from 2a to address path 5. f-
output to the tab bus 6, write command line 8, and PCENL line 51. At that time, the write command
The function of G/c is switched to use it as a parity generator and output odd or even parity bits to the parity line 10.

Then, when 3 is input to the parity slave with parity bit, it is the same as parity page master 1 /C14
In step b, a parity check is performed using the data and parity, and if an error occurs, error processing is performed.

At that time, the trigger is also the same as master 1 with parity, AND for write command, address match, and PCENL signal.
This is done under condition 53b. When the slave 4 with no parity is accessed for write, a parity error will not occur even if there is no parity since the slave 4Vc with no parity does not have a parity check function.

When the parity page slave 3 is read accessed by the parity-less master 2, the address is output from the address generation circuit 11b, the data is output from the data generation circuit 12b, and the command generation circuit 13b outputs the address, and the parity page slave 3 has parity. Processing similar to data read from master 1 is performed. However, since the non-parity master 2 does not have a parity check function, it does not cause a 7<IJT error and only reads data. Therefore, even if the slave 4 without parity is read, only data will be read. Mabun,
In the case of write access, only the data of the non-parity master 2 is input to the parity page slave 3 and a parity check is performed, but since the PCENL signal is inactive, the data is not determined to be abnormal. In addition, when write accessing slave 4 without parity, even if parity is not added, there is no parity check function, so a parity error will not occur. If you use a device with information on it, then
By waiting for 1 bit of information in the same way as the CENL signal,
In addition, a parity generator/checker IC (e.g. IC
8280, IC8280) can be provided with a PCENL terminal, and if that terminal is inactive, it can be configured so that it outputs a valid signal as an output and does not output it as an error.

〔Effect of the invention〕

As explained above, this invention is configured so that a PCENL (parity check enable) signal can be outputted to the bus parity check circuit, so that it is possible to distinguish between a circuit that waits for the parity check circuit and a circuit that does not wait for the parity check circuit.
It has excellent RGT effects, such as the ability to mix circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional bus parity check circuit. In the figure, 1 is a parity page master, 2 is a non-parity master, 3 is a parity page slave, 4 is a non-parity slave, 5 is an address bus, 6 is a data bus', 7i command line, 8H write command line, 9i ACK line, 10 is a parity line, 51 is a PCENL signal (harness check enable signal line, 52a,
52 biPcENL generation circuit (parity check enable generation circuit), Afl common bus (path). Note that the same reference numerals in each figure indicate the same or corresponding parts. Patent applicant: Mitsubishi Electric Corporation - Misaki Suimei (No.
No. 2, Koreaki's name Bus parity check circuit 3 Person making the amendment Representative Moriya Shiki 5, Target of amendment 6, Details of amendment uF are corrected as follows.

Claims (1)

[Claims] Connected to a common bus, addresses, data,
In a bus parity check circuit configured by multiple masters or multiple slaves such as a CPU, memory, or I/O port that outputs a command, an enable for determining whether or not a parity check can be executed for data on the common bus. A bus characterized in that the master or slave equipped with a parity check generation circuit that outputs signals in both directions toward the common bus line and the master or slave not equipped with the parity check generation circuit can coexist. Parity check circuit.