JPS6185819A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6185819A
JPS6185819A JP20866784A JP20866784A JPS6185819A JP S6185819 A JPS6185819 A JP S6185819A JP 20866784 A JP20866784 A JP 20866784A JP 20866784 A JP20866784 A JP 20866784A JP S6185819 A JPS6185819 A JP S6185819A
Authority
JP
Japan
Prior art keywords
insulating layer
main surface
layer
region
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20866784A
Other languages
Japanese (ja)
Inventor
Shiro Hine
日根　史郎
Satoshi Yamakawa
聡 山川
Masao Yamawaki
正雄 山脇
Masafumi Ueno
雅史 上野
Naoki Yuya
直毅 油谷
Masaaki Kimata
雅章 木股
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20866784A priority Critical patent/JPS6185819A/en
Publication of JPS6185819A publication Critical patent/JPS6185819A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76294—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using selective deposition of single crystal silicon, i.e. SEG techniques

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To form a deep oxide region for isolation in such a manner that an insulating layer having no stepping and a selective oxide region are linked together by a method wherein, using a selective epitaxial growing method, a narrow-widthed insulating layer is buried, and an oxide film is formed by performing a selective oxidizing method. CONSTITUTION:An insulating layer 2 is formed on the main surface of a semiconductor substrate 1, the insulating layer 2 is left in the prescribed region by performing a photoetching method, and the width of the insulating layer 2 is formed in 2mum or below. An epitaxial growing layer 3 having the film thickness enough to bury the insulating layer 2 is formed by performing a selective epitaxial growing method. The layer grown on the insulating layer 2 is thinly formed, and a structure wherein the insulating layer 2 and the oxide film 4 are linked together is obtained.

Description

【発明の詳細な説明】[Detailed description of the invention]

［産業上の利用分野］ この発明は半導体Ｒ’ｆ１、待に、半導体基板上の所定
の領域に形成されたｆｆｉ　ｆｉｔ　ｌ１ｆｆをエピタ
キシャル成長法を用いて埋め込み、埋め込まれた絶ｆ１
校上にあるエピタキシャル成長門を遍択口化法を用いて
酸化Ｒ９とすることにより深い分な用杷縁庖を設けた半
導体装置に関する。 ［従来の技悄］ ｍ　３　Ａ図ないしｍ３０図は従来行なわれているね緑
居を半導体基板（ウェハ）の主表面上の所定の領域に残
し、半導体基板の露出した主表面上にエピタキシャル成
長法を用いて選択的にエピタキシャル層を形成する半導
体装置の製造工程を示す図である。以下、図に従って、
従来の半導体装はのＩｊ！１ｍ工程について説明する。 第３Ａ図において、半導体基板（ウェハ）１の主表面上
にｆＯ縁ｎ２が形成される。第３Ｂ図において、写真ｎ
剣法によって半導体基板（ウェハ）１の主表面上の所定
の領域にのみ絶１ｔ！！２が残され、所定領域以外の基
板１の主表面は露出される。 第３Ｃ図において、選択性および平坦性に優れ、かつパ
ターンシフトの少ない減圧下のエピタキシャル成５法を
用いて、半で体皇仮１の雪山した主表面上に選択的にエ
ピタキシセル１３を形成する。 第３Ｄ目ｉ二おいて、通常の選択[Industrial Application Field] The present invention involves embedding a semiconductor R'f1, firstly, an ffi fit l1ff formed in a predetermined region on a semiconductor substrate using an epitaxial growth method.
The present invention relates to a semiconductor device in which an epitaxial growth gate on a substrate is oxidized to R9 using a selective opening method to provide a deep groove. [Conventional Techniques] Figures m3 A to M30 show the conventional method of epitaxial growth on the exposed main surface of a semiconductor substrate (wafer) by leaving a green layer in a predetermined area on the main surface of the semiconductor substrate (wafer). FIG. 3 is a diagram showing a manufacturing process of a semiconductor device in which an epitaxial layer is selectively formed using a semiconductor device. According to the diagram below,
The conventional semiconductor device is Ij! The 1m process will be explained. In FIG. 3A, an fO edge n2 is formed on the main surface of the semiconductor substrate (wafer) 1. In FIG. In Figure 3B, photo n
Kenpo is used to attack only a predetermined area on the main surface of the semiconductor substrate (wafer) 1! ! 2 is left, and the main surface of the substrate 1 other than the predetermined area is exposed. In FIG. 3C, epitaxial cells 13 are selectively formed on the snow-covered main surface of the main surface of the body 1 by using a reduced-pressure epitaxial growth method with excellent selectivity and flatness and with little pattern shift. . 3rd D i2, normal selection

【フ化技１ｆｉによっ
て、選択エピタキシャル成長層３の周辺Ａ戚がａ化され
てｒ：２化藝４となり、ｉａ　ｉｔ　ｎ　ｊｌが形成さ
れる。 ［発明が解決しようとする間口点〕 従来の貰７１は、上述のように１成されているので、第
３Ｄ図に示される鎖酸１０（笥吟層と５’ｓ択ｉ化つと
ｂＳ　ｌらなる壜ｔ′ｔ）の段すが第３Ｃ巳に示される
状序よりも大きくなるという不都合があった。 この発明の目的は上述の欠点を除去し、選択ｎ】化原領
Ｊ１における大きな段芒をなくした潔い分１用絶τゑ憤
−を有する半導体ス言を提供することでおる。 し問題点を解決するための手段］ この発明にかかる半に体電言においては、半群体基への
主表面上の所定ｎ域に穂縁膚を形成し、この（う、この
治ｔ＋　ｎを選択エピタキシャル成長法により形成され
るエピタキシャル成長層で完全に埋め込み、Ｃ１管に還
択配化法によりｌｒ、縁ｎ上のエピタキシャルＦｉｉ艮
ｆｆｌを１沢繭化して、αい分門用を０禄ｒ１戚を形、
伐する。 ［作用］ 選択性および平坦性に−れ、かつベターンシフトの少な
い選択エピタキシャル成良法を用いてエピタキシャル層
を成長させ、絶縁層を完全に埋め込んだ後、治縁膚上に
位ゴするエピタキシャル層を選択Ｃ１化しているので、
Ｑ　ｎのない平坦な深い９門用ｔＱ　縁ｅＱ　Ｒが形成
される。 ［ｊ−ｊ％何］ 第２Ａ図ないし第２Ｄ図は、この発明による第１の実施
例による半Ｊ体装コの製造工程を示す図である。以下、
ｍ２Ａ図ないし第２Ｄ図をＩ！照して説明する。 第２八因において、半豊体３：Ｓ坂１の主表面上に治縁
門２が通常の方法で形成される。第２Ｂ図において、写
真蝕刻法を用いて、半導体！５（ａｌの主表面上の所定
の領域にのみ？！！縁門縁厚２成される。 第２Ｃ図において、既に形成されている℃縁ｍ２を十分
に埋め込むに足る膜厚を有するエピタキシャル層３が形
成される。ａ２Ｄ図において、τ３禄門２の上にイ１２
實するエピタキシャル層がｉＪ　ＪＲ６ｉ化されて、５
所定の中３を有Ｖ８台化で１４が形成される。 以上のような（ｎ成にすれば、平坦で段荘のないロ択悶
ｔ：コ１゛１戚が形成される。しかし、上述のｊ）合、
モ縁−１２の１」が広いと、澄：二層２どコ化ｔ９４と
の間に完全に繭１ヒされないｆ４４５が形成され、深い
弁口用１′ご吟４１戎が）形成されない欠点がある。 上；３の欠点は祐禄で２のぐ】が広く、完全にｔｖ！禄
門２と埋め込むのに時間を翻し、エピタキシャル層のＦ
　７　、ｊメツくなることに１京口がある。したがりで
、”ｌ！　ｌ’ｆｉ　ｉｊの？Ｊを？くすれば、エピタ
キシャル門ノ＝”、ＩＯＩＪ’　；Ｄ　＜’＝　’Ｊ、
ヨ択ｒ２七ｂ”、　４　ト４ａ　ｄ　ｊ＋’！　２とが
ｊ’Ｕ　ｒ、Ｅ　シた深い分；°１用恰縁膜が（りられ
る。 第１へ図ＧいしむＶＤ図（Ｊ：亡松；３の幅を秋くし、
′；゛μト″１１ホＱ、７責の一°１角工程を示す図で
ある。以下、第１Ａ［１ないし；ｇ　１０図をひ照して
、この発明の第２の実Ｌ５　ｆ′；１について説明する
。 コ１へ図：こｊ３いで、従来法と同（ｋにして、半導体
すへ１の土Ｊ＜面上（ど、：こ縁ｆご２がＪｌｊ　ｉｉ
Ｊれる。第１Ｂ図において、写真ｒ３刻法によって基板
１の主表面の所定の饋ぺにのみ？ご縁ｎ２が残される。 ここで、第１の実ｙ５倒と異なりで緑ワ２の幅が２μｍ
以下に限定されている。第３Ｃ図において、選択エピタ
キシャル成長法により、既に形成されているｒ０縁門２
を十分に埋め込むに足る膜厚を右するエピタキシャル成
長ｎ３が形成される。ｔ３縁盾２と同等の１７？に達し
たエピタキシャル層は、厚８方向と門方向（絶ｔ’Ｑ！
！１２の幅方向）とへのＲ品成長により、第１Ｃ図に示
されるような連続したエピタキシャル層３が形成される
。このとき、ｊ０代ｎ２の幅が狭ければ狙いほど、ｔＯ
縁唐２を完全に埋め込むために必要なエピタキシャル層
の内がが薄くて済む（ｆ７さ方向のエピタキシャル成長
速度はクコ方向のエピタキシャル成員３！！度より大き
い）。したがって、第１Ｃ図に示される完全に埋め込ま
れた￥Ｑ　Ｑ　Ｉ″Ｊ２上のエピタキシャル成長層の厚
みは、第２Ｃ口に示される第１の実筋例よりも薄くなる
。第１Ｄ図において、７３　ｆｔ　ｍ　２上に位コする
エピタキシャル成ＱＩ７′ｉが３ゴ択門化されてｍ化ｆ
ｆ７４が形成される。このとき、第２Ｄ図に示される第
１の実ＬＰ５例と異なり、ｊｊ　ｉ！　ｎ　２と悶化駁
４とがつながった（ユ造が実現されている。 上述の実ｆｌ”１ｉ７１に示される！＋ｌ　：”ｊを右
する半導体装置はシリコン半に体装口全ｔ、９に適用で
きることはごうまでもない。また、基板のシ、″を電型
とエピタキシャル門の５電型とは同一であっても異なっ
ていても問題はないことは８つまでもない。 ［効！！！］ 以上のように、この発明にかかる半導体装置においては
、平坦性、選択性にｉれ、かつパターンシフトの少ない
逗択エピタキシャル成長法を用いて、幅を従来より狭く
した絶縁層を完全に埋め込み、その１升、這択口化法に
より所定の領域に這択口七口を形成しているので、平坦
で段丘のない、かつ治縁ｎと遣択口化領域とがつながっ
た深い分１″′を用絶縁内域が形成される。[By the oxidation technique 1fi, the surrounding area of the selective epitaxial growth layer 3 is converted to a, r:2 conversion 4, and ia it n jl is formed. [Interface point to be solved by the invention] Since the conventional filter 71 is constructed as described above, the chain acid 10 shown in FIG. There was an inconvenience that the steps of the bottle t't) were larger than the order shown in the third C. SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a semiconductor device which eliminates the large step in the selection area J1 and has the advantage of eliminating the need for a large step. [Means for Solving the Problems] In the hemisphere telegram according to the present invention, a panicle edge skin is formed in a predetermined region n on the main surface of the semicolony group, and this (um, this treatment t + n completely filled with an epitaxial growth layer formed by a selective epitaxial growth method, and cocooned the epitaxial layer on the lr and rim n by the recirculation method in the C1 tube, and made the α-portion into a cocoon. form a relative,
cut down [Operation] After growing an epitaxial layer using a selective epitaxial growth method that has good selectivity and flatness and has little betan shift, and completely embedding the insulating layer, select the epitaxial layer that will be placed on the healing edge skin C1. Because it has become
A flat deep nine gate tQ edge eQ R without Q n is formed. [j-j%] Figures 2A to 2D are diagrams showing the manufacturing process of a half-J body according to the first embodiment of the present invention. below,
m2A diagram or 2D diagram I! I will refer to and explain. In the second eighth cause, a fertile body 3: a healing gate 2 is formed on the main surface of the S slope 1 by a normal method. In FIG. 2B, a semiconductor! 5 (only in a predetermined area on the main surface of the al?!! Marginal edge thickness 2 is formed. In FIG. 3 is formed.In the a2D diagram, I12 is formed on top of τ3Rokumon2.
The actual epitaxial layer is made into iJ JR6i, and 5
14 is formed by converting the predetermined middle 3 into a V8 unit. In the case of (j) mentioned above, a flat and stepless locus is formed.
If the edge of 12 is wide, f445, which is not completely cocooned, will be formed between the clear and double-layered t94, and the deep valve opening 1' will not be formed. There is. Above: The disadvantage of 3 is Yuroku and 2 Nogu] is wide and completely TV! By changing the time for embedding with Rokumon 2, the F of the epitaxial layer is
7. There is a 1,000,000-way point in becoming a member. If you want to change the ?J of ``l!
Yo selection r27b'', 4 t4a d j+'! : Dead pine; fall width of 3,
It is a diagram showing a 1° 1 angle process of 11hoQ, 7th part.Hereinafter, referring to Figure 1A[1 to;g10, the second fruit of this invention L5 '; 1 will be explained. Figure 1: Here, the same as the conventional method (k, on the soil J< surface of semiconductor section 1 (Do,: this edge f go 2 is Jlj ii
I can do it. In FIG. 1B, only a predetermined area on the main surface of the substrate 1 is printed using the photo r3 engraving method. A relationship n2 is left behind. Here, unlike the first fruit Y5, the width of the green wire 2 is 2 μm.
Limited to: In FIG. 3C, the r0 marginal gate 2 already formed by the selective epitaxial growth method.
Epitaxial growth n3 is formed to have a film thickness sufficient to fully embed. 17 equivalent to t3 edge shield 2? The epitaxial layer that has reached the thickness is in the 8th direction and in the gate direction (absolute t'Q!
! 12), a continuous epitaxial layer 3 as shown in FIG. 1C is formed. At this time, the narrower the width of j0 generation n2, the more tO
The epitaxial layer required to completely bury the edge 2 needs to be thinner on the inside (the epitaxial growth rate in the f7 direction is higher than the epitaxial growth rate in the lateral direction). Therefore, the thickness of the epitaxial growth layer on the completely buried ¥Q Q I''J2 shown in FIG. The epitaxial growth QI7'i located on ft m 2 is converted into 3-go gate and becomes m
f74 is formed. At this time, unlike the first real LP5 example shown in FIG. 2D, jj i! n 2 and agonizing part 4 are connected (Yuzukuri is realized. As shown in the above-mentioned actual fl"1i71!+l: "The semiconductor device to the right of j is silicon half with the entire mounting port t, 9 It goes without saying that it can be applied to the 5-electrode type of the substrate and the 5-electrode type of the epitaxial gate, whether they are the same or different. [Effect! !!] As described above, in the semiconductor device according to the present invention, an insulating layer whose width is narrower than conventional ones can be completely grown using a selective epitaxial growth method that is superior in flatness and selectivity and has less pattern shift. By filling in one square, seven holes are formed in a predetermined area using the method of forming a hole, so it is flat and has no terraces, and a deep area where the edge n and the area where the area is formed is deep. An insulating inner region is formed for 1"'.

【図面の簡単な説明】[Brief explanation of the drawing]

第１八図ないし第１Ｄ図はこの発明の一実施例である半
導体装置の製造工程を示す因である。第２Ａ図ないし第
２ＤＩ７１はこの発明による半導体装置の原理的なｌ、
′１着工程を示す図である。第３八口ないし第３Ｄ図は
１毛来の半導体に口の製造工程を示す図であるっ 図において、１は半導体基板、２は絶縁層、３はエピタ
キシャル成長層、４は口化膜、５は選択酸化で酸化され
なかったエピタキシャルＭ　ｆη域、１０はｉＭ　ｆＩ
４域。 なお、口中、同符弓は同一または相当部を示す。FIGS. 18 to 1D show the manufacturing process of a semiconductor device which is an embodiment of the present invention. FIGS. 2A to 2D 71 show the principle l of the semiconductor device according to the present invention,
It is a diagram showing the first-place process. Figures 3 to 3D are diagrams showing the manufacturing process for semiconductors from 1 to 3. In the figures, 1 is a semiconductor substrate, 2 is an insulating layer, 3 is an epitaxial growth layer, 4 is an insulating film, and 5 is the epitaxial M fη region that was not oxidized by selective oxidation, and 10 is the iM fI
Area 4. Note that the same note in the mouth indicates the same or equivalent part.

Claims (2)

【特許請求の範囲】[Claims] （１）主表面を有する半導体基板と、 前記主表面上の所定の領域に形成される、狭い幅を有す
る絶縁層と、 前記所定領域以外の主表面上にエピタキシャル成長法に
より形成され、前記絶縁層を埋め込むエピタキシャル層
と、 前記絶縁層上に位置するエピタキシャル層が選択酸化さ
れた領域とを含む半導体装置であつて、前記選択酸化領
域と前記絶縁層とが連続して深い分離用酸化膜を形成す
る、半導体装置。(1) a semiconductor substrate having a main surface; an insulating layer formed in a predetermined region on the main surface and having a narrow width; and an insulating layer formed on the main surface other than the predetermined region by an epitaxial growth method; and a region where the epitaxial layer located on the insulating layer is selectively oxidized, wherein the selectively oxidized region and the insulating layer are continuous to form a deep isolation oxide film. , semiconductor devices. （２）前記絶縁層の幅は２μｍ以下であり、前記選択酸
化領域の幅は２μｍ以上である、特許請求の範囲第１項
記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the width of the insulating layer is 2 μm or less, and the width of the selective oxidation region is 2 μm or more.
JP20866784A 1984-10-04 1984-10-04 Semiconductor device Pending JPS6185819A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20866784A JPS6185819A (en) 1984-10-04 1984-10-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20866784A JPS6185819A (en) 1984-10-04 1984-10-04 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6185819A true JPS6185819A (en) 1986-05-01

Family

ID=16560055

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20866784A Pending JPS6185819A (en) 1984-10-04 1984-10-04 Semiconductor device

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JP (1) JPS6185819A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008180762A (en) * 2007-01-23 2008-08-07 Matsushita Electric Ind Co Ltd Optical axis adjustment device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4839181A (en) * 1971-09-22 1973-06-08
JPS53112685A (en) * 1977-03-12 1978-10-02 Toshiba Corp Semiconductor device and its manufacture
JPS59172247A (en) * 1983-03-18 1984-09-28 Sony Corp Manufacture of semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4839181A (en) * 1971-09-22 1973-06-08
JPS53112685A (en) * 1977-03-12 1978-10-02 Toshiba Corp Semiconductor device and its manufacture
JPS59172247A (en) * 1983-03-18 1984-09-28 Sony Corp Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008180762A (en) * 2007-01-23 2008-08-07 Matsushita Electric Ind Co Ltd Optical axis adjustment device

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