JPS6184894A - Solder printing method - Google Patents

Solder printing method

Info

Publication number
JPS6184894A
JPS6184894A JP20732484A JP20732484A JPS6184894A JP S6184894 A JPS6184894 A JP S6184894A JP 20732484 A JP20732484 A JP 20732484A JP 20732484 A JP20732484 A JP 20732484A JP S6184894 A JPS6184894 A JP S6184894A
Authority
JP
Japan
Prior art keywords
solder
printed
mask
printing
printing method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20732484A
Other languages
Japanese (ja)
Inventor
瀬野 眞透
義彦 三沢
白川 時夫
橋口 義信
進 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20732484A priority Critical patent/JPS6184894A/en
Publication of JPS6184894A publication Critical patent/JPS6184894A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、基板上の印刷パターンに半田を印刷す半田印
刷方法に関するものであり、基板上の印刷パターンの大
きさ、形状および半田印刷後に基板上に装着するチップ
部品の大きさ、形状に応じて一工程で同一基板上に同一
マスクを用いて適切な量の半田印刷を可能とする半田印
刷方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a solder printing method for printing solder on a printed pattern on a board, and the size and shape of the printed pattern on the board, as well as the amount of solder on the board after solder printing. The present invention relates to a solder printing method that allows an appropriate amount of solder to be printed on the same substrate in one process using the same mask depending on the size and shape of the chip components to be mounted on the board.

従来例の構成とその問題点 従来の半田印刷を第1図〜第4図により説明する。Conventional configuration and its problems Conventional solder printing will be explained with reference to FIGS. 1 to 4.

第1図は半田印刷からチップ部品装着、半田付(リフロ
ー)1での工程図である。
FIG. 1 is a process diagram from solder printing to chip component mounting and soldering (reflow) 1.

半田印刷方法人ではスキージ1と呼ばれるヘラを矢印X
方向に移動させ半田2をマスク3の印刷部分である抜穴
4より押し出して印刷回路基板(以下基板と呼ぶ)6上
の印刷パターンeに印刷する。次にチップ部品装着工程
Bではチップ装着機のチップ吸着ノズル7を矢印Y方向
に降下させ基板6上の印刷パターン6にチップ部品8を
装着する。最後にチップ部品の半田付工程C(リフロ一
工程)では半田2をランプ9によってリフローさせチッ
プ部品80半田付を行なう。
Solder printing method Use the spatula called squeegee 1 with the arrow
direction, the solder 2 is pushed out through the hole 4 which is the printed part of the mask 3, and printed on the printed pattern e on the printed circuit board (hereinafter referred to as the board) 6. Next, in the chip component mounting step B, the chip suction nozzle 7 of the chip mounting machine is lowered in the direction of arrow Y to mount the chip component 8 onto the printed pattern 6 on the substrate 6. Finally, in the chip component soldering step C (reflow step), the solder 2 is reflowed by the lamp 9 and the chip component 80 is soldered.

第2図に示すように、従来のマスク3の抜穴4は基板6
上の印刷パターン6と同形状でありマスク3の厚み10
によって印刷される半田量は決定されていたため、第3
図に示すように厚みが異なるチップ部品8,11.12
を同一基板6上に装着、半田付すると、正常な半田付状
態人や半田2の量が相対的に少ない状態B又は多い状態
Cが発生する。また第4図に示すように基板6上の隣接
している。印刷パターン13.14に半田2を印刷しチ
ップ部品16を装着、半田付すると回路短絡(ブリッジ
)16が発生し半田付不良となっていた。
As shown in FIG. 2, the hole 4 of the conventional mask 3 is
It has the same shape as the printed pattern 6 above, and the thickness of the mask 3 is 10
Since the amount of solder printed was determined by
Chip parts 8, 11 and 12 with different thicknesses as shown in the figure
When mounted and soldered on the same board 6, a normal soldering state, a state B in which the amount of solder 2 is relatively small, or a state C in which the amount of solder 2 is relatively large will occur. Further, as shown in FIG. 4, they are adjacent to each other on the substrate 6. When solder 2 was printed on printed patterns 13 and 14, chip components 16 were mounted, and soldered, a short circuit (bridge) 16 occurred, resulting in poor soldering.

この問題を解決するためには、基板上の印刷パターンの
大きさ、形状及び装着、半田付するチップ部品の大きさ
、形状により印刷用マスクが各々必要であり印刷工程も
多工程に及んでいた。
To solve this problem, each printing mask was required depending on the size, shape, and mounting of the printed pattern on the board, and the size and shape of the chip components to be soldered, and the printing process involved multiple steps. .

発明の目的 本発明は、前記問題点を解決するものであり印刷パター
ンの大きさ、形状及び装着、半田付されるチップ部品の
大きさ、形状に応じて一工程で同一基板上に同一マスク
を用いて適切な量の半田を印刷することを目的とするも
のである。
OBJECT OF THE INVENTION The present invention solves the above-mentioned problems, and it is possible to print the same mask on the same substrate in one process according to the size, shape and mounting of the printed pattern, and the size and shape of the chip components to be soldered. The purpose of this is to print an appropriate amount of solder.

発明の構成 本発明は、上記目的を達成するため、印刷用マスクの抜
穴を基板上の印刷パターンより大きく、又は小さくする
ことにより印刷する半田量を調整する方法であって、大
きさや形状の異なる印刷パターン及びチップ部品に応じ
て一工程で同一基板上に同一マスクを用いて適切な量の
半田を印刷可能なようにしたものである。
SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a method for adjusting the amount of solder to be printed by making the holes in a printing mask larger or smaller than the printed pattern on the substrate. This makes it possible to print an appropriate amount of solder on the same substrate in one process using the same mask according to different printing patterns and chip components.

実施例の説明 以下、本発明方法の一実施例を第6図により説明する。Description of examples An embodiment of the method of the present invention will be described below with reference to FIG.

前記半田印刷工程において印刷パターンの大きさ、形状
及びチップ部品の大きさ、形状に応じてマスクがどの様
に構成されているかを示す。
This figure shows how the mask is constructed in accordance with the size and shape of the printed pattern and the size and shape of the chip component in the solder printing process.

基板5上の隣接している印刷パターン1アに牛用印刷す
るためには、ブリッジ(第4図−16参照)の防止が必
要である。そこでマスク3の抜穴は印刷パターン17よ
り小さくした抜穴1Bのようにすれば、前肥り70一時
において半田の濡れ性により印刷ノ°ターン17全体に
半田が拡がり薄くなるためブリッジが防げる。またこれ
により予備半田も可能となる。
In order to print on adjacent printing patterns 1a on the substrate 5, it is necessary to prevent bridging (see FIG. 4-16). Therefore, if the holes in the mask 3 are made like the hole 1B which is smaller than the printed pattern 17, bridging can be prevented since the solder spreads over the entire printed pattern 17 due to the wettability of the solder and becomes thinner at the pre-filling stage 70. This also enables preliminary soldering.

次に。チップ部品の大きさく厚み)が異なるものを基板
6上の印刷パターン19 、20に装着、半田付する際
の適切な半田量を印刷するためにはチップ部品庫の薄い
ものについてはマスク1の抜穴を抜穴21のように印刷
パターン19より小さくし半田量を減少させ半田量過多
(第3図−〇参照)を防ぐ、またチップ部品庫の厚いも
のについてはマスク1の抜穴を抜穴22のように印刷パ
ターン2oより大きくし半田量を増加させ半田量不足(
第3図−B参照)を防ぐ。
next. In order to print the appropriate amount of solder when attaching and soldering chip parts with different sizes and thicknesses to the printed patterns 19 and 20 on the board 6, it is necessary to remove the mask 1 for thin chip parts in the chip parts storage. Make the holes smaller than the printed pattern 19 like punch holes 21 to reduce the amount of solder and prevent excess solder (see Figure 3 - ○). Also, for thick chip parts warehouses, make the holes smaller than the printed pattern 19. As shown in 22, the print pattern is made larger than 2o and the amount of solder is increased to avoid insufficient solder amount (
(see Figure 3-B).

発明の効果 以上のように、本発明の方法によれば、従来のような印
刷用マスクの厚みのみで半田量を調整し印刷する方法は
、基板上の印刷パターンの大きさ、形状及び装着、半田
付されるチップ部品の大きさ、形状により印刷用マスク
が各々必要であり印刷工程も多工程に及んでいたが、本
発明の方法では、印刷用マスクの抜穴を基板上の印刷パ
ターンより大きく又は小さくすることにより半田量を調
整するようにしたため、印刷パターンの大きさ、形状及
び装着、半田付されるチップ部品の大きさ、形状に応じ
て一工程で同一基板上に同一マスクを用いて適切な量の
半田を印刷することができる。
Effects of the Invention As described above, according to the method of the present invention, the conventional method of printing by adjusting the amount of solder only by adjusting the thickness of the printing mask is different from the conventional method of printing by adjusting the amount of solder only by adjusting the thickness of the printing mask. Printing masks were required for each chip component to be soldered, depending on its size and shape, and the printing process involved multiple steps. However, in the method of the present invention, the holes in the printing mask can be made from the printed pattern on the board. Since the amount of solder can be adjusted by making it larger or smaller, the same mask can be used on the same board in one process depending on the size, shape and mounting of the printed pattern, and the size and shape of the chip components to be soldered. It is possible to print the appropriate amount of solder.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半田印刷からチップ部品装着、半田付(リフロ
ー)までを示す工程図、第2図は従来のマスクの構成を
示す見取り図、第3図は従来の印刷方法によって印刷し
た状態を示す断面図、第4図は従来の印刷方法によって
基板上の隣接している印刷パターンに印刷しり70−し
た状態を示す  。 側面図、第5図aは本発明方法を取り入れた一実施例の
マスクの構成を示す平面図、第5図すは同断面図である
。 2・・・・・・半田、3・・・・・・マスク、5・旧・
・回路印刷基板、18,21.22・・・・・抜穴。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名b 第3図 第 5 図 17       IU/’1
Figure 1 is a process diagram showing the process from solder printing to chip component mounting and soldering (reflow), Figure 2 is a sketch showing the structure of a conventional mask, and Figure 3 is a cross section showing the state printed by the conventional printing method. FIG. 4 shows a state in which adjacent printed patterns on a substrate are printed by a conventional printing method. FIG. 5a is a side view, and FIG. 5a is a plan view showing the configuration of an embodiment of a mask incorporating the method of the present invention, and FIG. 5A is a sectional view thereof. 2... Solder, 3... Mask, 5 Old...
・Circuit printed board, 18, 21, 22...holes. Name of agent Patent attorney Toshio Nakao and 1 other personb Figure 3 Figure 5 Figure 17 IU/'1

Claims (2)

【特許請求の範囲】[Claims] (1)非印刷部分と印刷部分とから成る印刷用のマスク
を使用して印刷回路基板上に、半田の印刷を行う半田印
刷方法であって、前記マスクの印刷部分の面積を、装着
する部品の形状と印刷回路のパターン形状及び隣接ピッ
チにより印刷回路のラウンドの大きさに対して変化させ
たマスクにより半田印刷を行う半田印刷方法。
(1) A solder printing method in which solder is printed on a printed circuit board using a printing mask consisting of a non-printed part and a printed part, in which the area of the printed part of the mask is determined by the part to be mounted. A solder printing method that performs solder printing using a mask that changes the size of the round of the printed circuit depending on the shape of the circuit, the pattern shape of the printed circuit, and the adjacent pitch.
(2)マスクに設けられた印刷部分の内、予備半田を施
すラウンドに対応した印刷部分に対してはそのラウンド
の大きさより前記印刷部分の面積を小さくしたことを特
徴とする特許請求の範囲第1項記載の半田印刷方法。
(2) Among the printed portions provided on the mask, for a printed portion corresponding to a round to which preliminary soldering is applied, the area of the printed portion is made smaller than the size of the round. The solder printing method described in Section 1.
JP20732484A 1984-10-02 1984-10-02 Solder printing method Pending JPS6184894A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20732484A JPS6184894A (en) 1984-10-02 1984-10-02 Solder printing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20732484A JPS6184894A (en) 1984-10-02 1984-10-02 Solder printing method

Publications (1)

Publication Number Publication Date
JPS6184894A true JPS6184894A (en) 1986-04-30

Family

ID=16537872

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20732484A Pending JPS6184894A (en) 1984-10-02 1984-10-02 Solder printing method

Country Status (1)

Country Link
JP (1) JPS6184894A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016869A (en) * 1973-06-20 1975-02-21
JPS5555598A (en) * 1978-10-19 1980-04-23 Nippon Electric Co Method of soldering to printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5016869A (en) * 1973-06-20 1975-02-21
JPS5555598A (en) * 1978-10-19 1980-04-23 Nippon Electric Co Method of soldering to printed circuit board

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