JPS6180072A - Apparatus for processing module information of lsi test system - Google Patents

Abstract

PURPOSE:To make it possible to search the error status, when a module error is generated, at a high speed, by performing the soft processing of module information by one flag scanning and high speed address forming algorithm. CONSTITUTION:The PAGE data outputted to a PAGE bus from a page register 13 is incrementally added at every transmission cycle and the flag word of each measuring module is successively put on a DATA bus. A flag detection signal comes to HIGH when one bit or more of a flag was detected in the flag word and the input data of FIFO memory 32 is made effective. By performing flag word scanning as mentioned above, the page data of flag bit detection is stored in the FIFO memory 32 after the finish of scanning. An order module IM refers to an address table by using the lower rank three bits of the flag word data addressing the page data as an address and forms the page and address of module information.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a processing device that processes module information at high speed in an analog LSI test system. especially,
The present invention is characterized in that it is possible to search the error status and identification of the error-occurring module at eight speeds when a module error occurs.

(Conventional technology) FIG. 2 shows an example of an analog LSI test system.

The system includes a plurality of measurement modules MMI to M M n
and a command module IM for collectively controlling each module.

Each measurement module is composed of a voltage generation module, a voltage measurement module, etc., and the command module IM includes a page (PΔQE: data representing module NO0), an address (ΔDD: measurement module memory address command (CMD), data ( DATA) buses B+ to 8
3, it is possible to transfer data to and from the measurement module in both directions.

Here, module information means the data transferred from the measurement module to the command module, specifically the error status of each measurement module, module identification information (
type of module), etc. From the perspective of the command module, these ff5 reports exist in a fixed address area of the memory in the command module, regardless of the type of measurement module. An example is shown in FIG. In this case, module information exists in the area of addresses 9000-9009.

FIG. 4 shows an example of the hardware configuration of a conventional command module and measurement module. The command module is a standard C
It consists of a PU (central processing unit) 11, a memory 12, and an interface logic for controlling the measurement module. The interface logic is F)AG
Page register 3, A for controlling E-bus B1
Address register 4 for controlling DD bus B2
, connect DATA bus B3 to 1ldJ If only DM
A (Direct Men+ory Access
) DMA controller 5 for performing the transfer, and further DM
It consists of a counter 6 for incrementing the ADD bus during A transfer.

The measurement module includes a page decoder 21 for identifying pages allocated to each measurement module, a measurement module CPU 22, and a memory (read) or writeable by either the measurement module or the command module. (hereinafter referred to as measurement module/memory) 23.

(Problems to be Solved by the Invention) Usually, module information is taken into the command module by an interrupt from the measurement module.

□ In the conventional example, as shown in Figure 5, all module information (for each measurement module) was loaded into a memory area of 7 joules including the command.

In this case, the command module performs a soft scan of the entire memory area and retrieves the module information, regardless of whether there is module information or not. must be identified. The drawback was that it required a lot of time.

The object of the present invention is to provide a module information processing device that eliminates this slight drawback.

(Means for Solving the Problems) In order to achieve such an object, the present invention includes a memory for storing module information as well as a flag word indicating the presence or absence of module information in the S1 measurement module. The module also enables DMA for pages, and is equipped with a flag detector that detects flag words during flag word scanning, and a FIFO memory to store the page when a flag word is detected, and stores data in the FIFO memory and 7 lag words. Equipped with a means to generate module information addresses using blocks, one-time DMA transfer (flag scan) and high-speed address generation algorithm to perform software processing and data transfer of only necessary information, greatly reducing processing time. It is characterized by this.

(Example> The present invention will be described in detail below based on Examples.

FIG. 1 is a configuration diagram showing one embodiment of a command module according to the present invention. In this figure, parts equivalent to those in FIG. 4 are given the same reference numerals. 1, the difference from the conventional example shown in FIG. 4 is that the page counter 3 is configured so that DMA transfer is possible for not only ADD but also PAGE.
1 and for storing the page number of the module in which the module information exists.
st in first stout) memory 32 and flag word scanning (PAGE increment DMA
In the middle), a flag detector 33 for detecting bits of the flag word is omitted.

The measurement module is different in that a gA area for storing seven lag words is provided in the memory as shown in FIG. As shown in the figure, this flag word indicates the presence or absence of each module information in the measurement module in bit correspondence.

In FIG. 1, data is exchanged between a CPU 11, a memory 12, a DMA controller 15, a page register 13, an address register 14, and a FIFO memory 32 via a data bus .

The operation in such a configuration will be explained next. FIG. 7 shows a time chart during flag word scanning of the apparatus of the present invention. As shown in FIG. 3A, the PAGE data output to the PAGE bus B2 is incremented for each transfer cycle (page scan). On the other hand, the ADD data output to the ADD bus B2 is fixed (fixed address of flag word). The seven lag words of each measurement module are sequentially placed on the DATA bus B3.

The flag detection signal is the output signal of the flag detector, and D
When a flag word is sucked up from the AT△ bus B3 and a flag of 1 bit or more is detected in the flag word, a "HIG) bit" is generated as shown in Fig. 7 (2). The flag bit is detected in the cycle, and the flag bit is not detected in the cycle (2).

F[F○ Memory input data (PAGE data)
is valid only if the flag bit is detected. In the figure, pages (PAGE) in cycles ■ and ■ are shown.
1, PAGE3) is input to FrFO.

By performing flag word scanning in this way,
After scanning is completed, the FIFO memory and memory 12 of the command module are in the state shown in FIG. As shown in FIG. 8, the FIFO memory contains page data for flag bit detection, that is, page data where module information may exist (in the figure, 5.10, 35., . . .
) are stored serially. The command module refers to the contents of the memory (flag word) whose address is this page data. The ADD table is referred to using the lower 3 bits of the flag word data as an address, and 9003, for example, as shown in the figure is obtained. In this way, PAGE and ADD of existing module information can be easily generated.

With such a function, the command module can read module information in an extremely short processing time and with the minimum necessary number of transfers.

Figure 9 shows the measurement module up to module information transmission,
The flow of operation of the command module is shown.

(Effects of the Invention) As explained above, according to the present invention, the entire information area D
Module information processing, which used to take a lot of time for MA transfer and soft scan of all information areas, has been reduced to a single DMA transfer (
By performing software processing using a flag scan) and high-speed address generation algorithm, and by transferring only necessary information, processing time can be significantly reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a command module in an analog LSI test system according to the present invention, FIG. 2 is a block diagram of a conventional analog LSI test system, and FIG.
The figure is a diagram for explaining the memory configuration and module information of the Otsu 1 measurement module as seen from the command module in Figure 2. Figure 4 is a configuration diagram of the conventional command module and measurement module shown in Figure 2. The figure is a diagram for explaining the storage state of module information taken into the command module in the system of Figure 2, and Figure 6 is an explanatory diagram for explaining the memory configuration of the measurement module of the present invention. 8 is a time chart for explaining the operation, FIG. 8 is a diagram for explaining the state of the FIFO memory and memory of the command module after flag word skimming, and FIG. 9 is a diagram for explaining the measurement, module, and command up to module information transmission. This is a flowchart showing the operation of the module. 1M...Command module, 11...CPIJ, 12
...Memory, 13...Page register, 14...
- Address register, 15... DMA controller, 16... Address counter, MM... Measurement module, 21... Page decoder, 22... CP
U, 23...Measurement module memory, 31...Page counter, 32...FIFO memory, 33...Flag detector. Figure 2 Figure 3 Figure 5

Claims (1)

[Claims] Consisting of a plurality of measurement modules including a voltage generation module, a voltage measurement module, etc., and a command module for collectively controlling each module, the command module is used for pages, addresses, commands, and data. Each bus B
In an analog LSI test system that enables bidirectional data transfer to and from a measurement module through _1 to B_3, the measurement module includes a memory for storing module information as well as a flag word indicating the presence or absence of module information; The command module also enables DMA for pages, and includes a flag detector that detects flag words during flag word scanning, and a FIFO memory for storing a page when a flag word is detected, and stores data in the FIFO memory and flags. A module information processing device for an analog LSI test system, comprising means for generating module information addresses using word blocks.