JPS617953A - Memory device - Google Patents

Abstract

PURPOSE:To decrease the load of software of a system, and to increase a processing speed of a sequence operation by providing a memory of pack and unpack processings and a controlling circuit. CONSTITUTION:An input data from a process having the information at a bit unit is unpacked and saved in a memory 26 through a buffer 22 from a bus B under the control of a controlling circuit 24. When executing a sequence operation, it is read out as a data having information at a byte unit from the memory 26. An information bit read out of the memory 26 is selected under the control of a controlling circuit 28. As a result of the sequence operation, only one bit in the information of the byte unit is made significant and written in a memory 27. In such a case, an address of the write bit is selected under the control of a controlling circuit 29. An output data has information at a bit unit under the control of the circuit 29, and it is read out of the memory 27 as a packed data, and written in an output device.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a mesori device having a built-in function of packing and unpacking digital information.

[Conventional technology]

Figure 1 shows, for example, JP-A-57-10852 and JP-A-5.
7-162193, a block diagram showing a schematic configuration of a conventional memory device. In the figure, 1 is a decoder that decodes addresses from system bus B, 2 is a buffer that exchanges data with system bus B, 3 is a memory, and 4 is a control circuit that responds to control (commands) from system bus B. . In addition to this, peripheral circuits (not shown) are added.

Next, the operation will be explained. Here, a case where the memory device is applied to a system that performs sequence calculation processing will be described.

First, when digital data having digital information in bits is input from a process (not shown), it is temporarily stored in the memory 3 via the system bus B and the buffer 2. In other words, the system bus B is
The above digital information is developed in byte or word units, that is, unpacked (UNPACK) and stored in the L memory 3.

After performing sequence calculations using this expanded digital information, the results are stored in the memory 3.

The digital information in 30 bytes or word units of memory is then integrated and processed by software processing so that it has information in bit units, that is, it is backed up (PACKed) and output to the process after death.

FIG. 2 is a flowchart showing the sequence calculation process described above.゛Since conventional memory devices are configured as described above, 1. When applied to a system that performs sequence operations, backing and unpacking processing is required as software processing, and a non-negligible amount of processing time is required due to the software load. There was a drawback.

[Summary of the invention]

This invention was made to eliminate the above-mentioned drawbacks of the conventional ones, and by providing memory and control circuits for backing and unbacking processing, it reduces the software load of the system and increases the processing speed of sequence operations. An object of the present invention is to provide a memory device that can increase the performance.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 3, 21 is a buffer for receiving and receiving addresses from system bus B, 22 is a buffer for data exchanged with system bus B, 23 is a decoder for decoding the address of buffer 21, and 24 is a control command from system bus B. 25 is a write/read address selection circuit, 26 is a memory for unback data, 27 is a memory for back data, 28 is a control circuit for unback bits, and 29 is for back bits. This is the control circuit.

Next, the operation when the memory device according to the present invention is applied to sequence operations will be explained.

0) First, input data from a process having information in bit units is anobacked and saved in the memory 26 from the system bus B via the buffer 22 under the control of the control circuit 24.

←) When performing a sequence operation, the data is read out from the memory 26 as data containing information in units of sibytes.

At this time, the information bits read from memory 26 are selected under the control of control circuit 2B.

The result of the f→ sequence operation is written to the memory 27 with only one bit of byte-based information being significant. At this time, the address of the write bit is selected under the control of the control circuit 29.

The output data to be output to the process has information in units of p bits under the control of the control circuit 29, is read out from the memory 2T as backed-up data, and is written to an output device (not shown).

The memory addresses necessary for the above sequence operation can be set separately by the decoder 23 for each of the input data, up-loaded input data, sequence operation result data, and output data. Further, writing and reading control for each memory area is performed by a decoder 23, a control circuit 24, and a selection circuit 25. The sequence calculation process described above is shown in a flowchart in FIG.

In the above embodiment, the memory device is provided with back and unback functions, but the same effect can be obtained even if the process input/output device is provided with back and unback functions.

〔Effect of the invention〕

As described above, according to the present invention, by providing a memory and a control circuit for unbacking and backing processing, backing and unpacking processing in sequence calculations can be omitted, and the load on calculation processing can be reduced. There is.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional memory device, and Figure 2 is a block diagram of a conventional memory device.
FIG. 3 is a block diagram of the memory device according to an embodiment of the present invention, and FIG. 4 is a flow chart of the operation of the memory device shown in FIG. 1.23...Decoder, 2,21.22...Buffer, 3,26.27...Memory, 4.24.28゜2
9... Control circuit, 23... Decoder. In addition, in the figures, the same reference numerals indicate the same parts.

Claims (1)

[Claims] a first memory that stores data having information in bits at a set address, and reads the data expanded in bytes from the set address;
To store data read from the memory in a set area, and to control access to the data in the second memory and the first and second memories, which are read from the area in a form having information in bit units. A memory device comprising: a plurality of control devices;