JPS61786A - Electronic machinery - Google Patents

Abstract

PURPOSE:To prevent the erasion of memory content used in a circulatory manner by an inadvertent operation, by operating an operation means at the coincidence time of the weekly time information and time information of a memory means and controlling the resetting of the memory means through the gate responding to the specific information of the memory means. CONSTITUTION:When the weekly time information and time information of the memory R1 of a series shift register through AND gates AG1, AG4 are coincided with each other, the output of a coincidence circuit CON1 comes to H and a means OUT such as a buzzer is operated. This means OUT is reset by a reset signal RSTK and the content of memory 2 is cleared through the AND gate AG6 which is opened by the signal RSTK, the coincidence signal of the daily time information and time information, DATA2 of the memory 2 same to that of the memory 1 by a coincidence circuit CON2 and a timing signal TX. Then, the coincidence output of the circuit CON2 is not generated on and after and the gate AG6 is held as it is closed and the memory R1 is not cleared by an inadvertent operation.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device that can repeatedly operate a plurality of days of the week information every week.

In conventional calculators, when you want to use data whenever you like, you either store the data in a so-called independent memory, or you use it once and then use it again. -1- The key to clear the memory contents was pressed incorrectly.

You may accidentally clear data that you want to use again.

In view of the above points, the present invention provides an electronic device that prevents the contents of a memory from being erased due to careless key operations.

Another object of the present invention is to store specific information in pairs with a plurality of days of the week data in a memory in order to prevent data from being cleared by careless key operations, and when the clear memory key is operated, the next day of the week data is stored in a memory. The present invention provides an electronic device that can be set to operate repeatedly every week.

Another object of the present invention is to store a scheduled time in a memory device in an electronic device having a clock function, and when the scheduled time is reached, generate a warning indicating that the scheduled time has been reached. This is means for resetting the warning, and the operation is repeated every week based on the scheduled time stored in the memory at the same time.

Other objects of the present invention will become clear from the description of embodiments given below in conjunction with the drawings.

Figure 1 is an external view showing one embodiment of an electronic device according to the present invention.

In the same figure, rOJ, rlJ, ~, "9" and "
φ” is a numerical key 1 for inputting numerical information. rXJ,
r÷J, r+'', r-J is the key that gives instructions for four arithmetic operations, STO is the key for writing data to the aforementioned independent memory, RCL is the key for calling data from the aforementioned independent memory, CM is the aforementioned key. The key to clear the contents of independent memory, C is the key to clear the contents of memory other than the above-mentioned independent memory, = is the four arithmetic operations rX", r÷", r
Keys for executing the commands ``+'' and ``r-'' and SK are keys for inputting information to prevent the contents of the above-mentioned independent memory from being cleared by the operation of key CM.

FIG. 2 is a block diagram showing the main parts of the electronic device shown in No. 11Z.

M is a memory, and here a multi-bit serial shift register is used as an example.

A memory that reads data from or writes data to the memory by setting address information, such as RAM (R
ANDOM ACCESS MEMORY) may be used.'' The two series of memories M store information in the following order. Specific information for determining whether to cause Fl to clear the memory contents is stored. Here, the logical value ``'l'' is used as such specific information. F2 to F9
The data is stored in the order of ~F9. In the illustration, since "rl" is stored in Fl, this indicates that a plurality of data "0OJ1...0IOIJ" stored in F2 to F9 are used.The information contents of memory M are changed by the clock to F9, F8, . . . is sequentially shifted in the direction of Fl. Note that this memory M is the exclusive memory in the aforementioned calculator.

IN] is an input device that detects the operation of the memory clear key CM provided on the calculator, also detects the timing signal TX, and inputs a logical value rlJ to the assigned line SL once during one operation of the key CM. Output a signal.

CCI is a control device that synchronizes with No. 4?4 from the input device INI and outputs a signal to the signal line S3 depending on the presence or absence of the signal on the signal line S2. Normally, a signal of 1srlJ is output here.

Gl is an AND gate, which controls the storage of data DATA from another memory into the memory M from one input terminal in accordance with the operation of the data write key STO and the signals generated by the operation of the numeric keys "0" to "9".

G2 is an AND gate that controls whether or not to save the contents of the memory M, and is connected to the write signal line WRI T.
When E is “L” by operating the key STO, the inverter ■
As a result, "l" of the signal line WRITEJ- is inverted to °°O', closing the gate (G2) and preventing the data in the memory M from returning from Fl to FIO.

When the signal on the write signal line WRI TE I- is '0', the signal l' is turned into an ant game by the inverter I.
2, the data in memory M is applied to ant gate G.
2. Of course] Two-mentioned AND gate G
2 has a terminal that receives a signal from the control device CCI, so in the explanation of 1-statement, the control device CCI is “1”.
Assume that a signal of ° is output.

OG3 is Orgate, Antoge-1Gl.

The output of G2 is sent to memory M.

G3 is an at gate, and here, this AND gate is used to determine whether or not the data in the memory M should be cleared. As mentioned above, for example, information on whether data in the memory should be erased or left is stored in Fl of the memory M, and such information can be accessed by key operation or internal 1
The control circuit determines the type of data and stores it in Fl. For example, it is assumed that the information leaves °゛l゛ and clears O゛. The data of such Fl is
) A signal T that becomes “1” when applied to G3
X is applied to the other input of AND gate G3. Therefore, at-gate G3 is ゛°0°゛” according to the output of Fl.
1” output, just like the output of Antogame 1/G2!!
When 1iS2 is °゛1'°, the control device CCI sets the signal on the signal line S3J2 to 1, opens the anchor G2, and circulates the data in the memory M2.
The contents of the signal line S2 are not cleared, and the signal on the signal line S2 is 0°.
At this time, the control device CC1 sets the A word line S3 to "0",
Close Antogame 1 and G2. Therefore, the data in memory M is not rotated and the data in memory M is cleared.

” - The operation of the embodiment constructed as described above will be explained.

Now, one of the numeric keys "0" to "9" in FIG. l or key S as shown in <Fl>
They are arranged via the signal line DATE by the write signal of TO. Such human power may be provided by known key human power controls.

The contents of memory M are attested to G by the clock CLOCK applied to the memory when no key operation is performed.
2 from F9 to F8 .・・・・・・F
l, cycle and shift to F9. Each time the specific information stored in Fl is shifted to F9, a 7th node T-to G3 is opened on the signal line TX as shown in FIG.
It is applied by a signal generating means of Shingin or Fuzusho, and it is determined what the specific information is. In this case, since the special information is "1", a signal of "1" is generated on the signal line S2. However, the control device CCI is the key CM from the human power device INI.
Since the signal obtained by the operation of (INI output in Figure 3) cannot be obtained, the output continues to output the rlJ signal. Therefore, antenna (K) G2 is not closed and the contents of memory M continue to circulate.

4. When the key CM is operated as an unnecessary and samurai key operation, the human power device TNI responds to the signal "1" on the signal line TX, and the signal L is output as shown in the figure for the time when the contents of the memory M are circulated once. is output. If the aforementioned data is in the memory M, when a signal of "1" appears on the signal line TX, the output of the AND gate G3 becomes rlJ as described above, and the control device CCI receives the signal of 1 from the input device INl. It receives the rlJ signal on the signal line S2 and outputs a signal of 1. If the specific information stored in Fl is "0" and the clear key 〇M is pressed, when a signal of 1 is applied to the signal line TX, a signal of O is applied to the signal line S2, The control device cci detects the signal 0 on the signal line S2 based on the "1" signal received from the human power device INI, outputs the O signal for one circulation time of the memory M, and closes the computer (game) G2. , clears the contents of memory M. The contents of the memory can be rewritten by writing as described above.

FIG. 4 is a block diagram of another embodiment according to the present invention.

In this embodiment, the scheduled time is stored in the memory in the electronic device, and when the scheduled time is reached and a warning is generated, the warning is reset by the warning reset means and the scheduled time is erased according to specific information stored together with the scheduled time. It is for determining whether or not to allow it.

To explain further by giving an example, when information on one car per hour and late time information can be generated manually, the date and time information is often only for that time, and the late time information is often a regular schedule. Therefore, the date and time information should be cleared by the reset key, but it is better not to clear the week and time information.

However, the date information here refers to information that does not include the year and month.

In FIG. 4, R1 is a memory, which has a configuration as shown in FIG. 5. The data input/output control is the same as in the embodiment shown in FIG. 2; data is written using the signal line SM, and the circulation of the contents of the memory M is prevented by the signal on the signal line RST, and the data is cleared. It is something.

The data arranged in the memory R1 is stored as shown in FIG. 6, for example. At the Fl position, 1 is stored as week information or 0 is stored as H row information. When 1 is stored in Fl, F2 to F8 are treated as week information, and rlJ is stored in F2.
G1 is °, I-], if F3 has "rl", the month, ・
...If "1" is present in F8, it means that soil is stored. If you remember Fl or "0".

F2 to F8 are H line information, 1 with 11 in F2 to F4.
The 0's digit value is stored, and the 1's digit value with 11 is stored in F5 to F8.

F9-F19 memorize the time with F9-F13, F J,
4 to F19 to store the minutes. In the figure, a plurality of day of the week information and time information of 2:08 are stored in R1.

R2 and R3 are memories and have the same configuration as R1.

AGI-AC3 are ant gates that transfer the contents of the memories R1 to R3, respectively, and timing signals Tl-T3 as shown in FIG. 7 are applied to each gate. Timing signals T1 to T3 are input to memory R1 to R3, respectively.
With a signal that is "l" during the circulation time (l w or d time).

This is obtained by a signal generating stage (not shown).

OR1 is an OR gate that serves to transmit the outputs of ANDK) AGI to AG3 to the next stage.

AC3 is an ant gate which allows the output of ORI to pass through in response to a timing signal TA as shown in FIG.

CON 1 is a coincidence circuit to which current late time information DATA 1 sent from a clock means (not shown) is applied via a reference p@sian gate AG4.

It has a function of comparing the contents of the memories R1 to R3 and detecting the information with 11 identified by the timing signal TX as shown in FIG. 7 using an AND gate or the like.

AC3 is an ant gate that passes the data output from ORI at timing TB in FIG.

CON2 is a coincidence circuit that refers to the time information with 1" outputted from a clock means (not shown) and compares it with the data in the memories R1 to R3 sent via the AND gate AG5, and also outputs the timing signal TX. The week information is identified using an AND gate or the like.

OR2 is an OR gate and is a -number circuit C0NI.

The coincidence output of CON2 is passed through to drive a warning means such as a buzzer sound generating circuit OUT.

AC3 is an ant gate which inputs the number circuit CON2, the timing signal TX, and the signal of the means (key or control circuit) for clearing the warning-r stage, and outputs ■ when all are 1.

AG7 to AG9 are AND gates, and timing signal T1
~ One shot output l of AND gate AG6 by T3) O51 ~ OS 3 Ni transmission, one shot 031-O
53. One shot) O51-053 are connected to signal lines R3TI-R3T, 3 of memories R1-R3, respectively, and clear the contents of the memory. One shot 0
The outputs of 31 to O53 are signals that become "1" during the IWORD time.

Now, to explain the operation of the embodiment consisting of the configuration 1- below, memory R1 stores a plurality of days of the week information and time information [data for 2:08] as late time information, and memory R2 stores time information with H. It is assumed that the data of 5:15 on the 30th of the information is stored.

Now, - the contents of memory R2 and the current H in several circuits CON2
When the visiting time information DATA2 matches, it is assumed that the matching circuit CON2 is output at the timing T2.TX, and the reset signal R3TK is outputted from the ant gates AG7 to AG9 through the AND gate AG6 at the timing T2TX. applied to one end, timing signal T1
〜Rl from AND gate AC3 by AND with T3
J signal is output, one shot O32 or IWORD
A signal of time "1" is output to signal 1i RS T 2. Therefore, the contents of memory R2 are 1 of 1 in O32.
The signal is not recirculated and its contents become all O's. Further, the reset signal R3TK resets the oath of the buzzer sound generating circuit OUT.

Next, when the contents of the memory R2 are led to the -.match circuit CON2 at timing T2, no coincidence output is output because the contents of the memory R2 are all O's.

On the other hand, the coincidence circuit CON l indicates that the moon clear 2:08 stored in the memory R1 matches the current late time information DATA1.
As it turns out, at the time of Tl/TX, OR2)
6 to drive the buzzer sound generating circuit OUT via
If it is determined by ON 1, the buzzer sound generation circuit OUT is driven via the OR game hOR2 at the time of TlφTX. As described above, the late time information can be identified by the matching circuit CON 1, and the operation can be performed repeatedly every week based on information on a plurality of days of the week.

As described above, the electronic device according to the present invention is configured to repeatedly operate every week with a plurality of days (-1) set to 1 to 1 in the stored data, so there is no need to reset the data.

[Brief explanation of the drawing]

Fig. 1 is an external view of an electronic device according to the present invention, Fig. 2 is a block diagram of an embodiment according to the present invention, Fig. 3 is a signal waveform diagram, and Fig. 4 is a block diagram showing another embodiment according to the present invention. , Fig. 5 is a detailed diagram of the memory shown in Fig. 4, and Fig. 6 is an explanatory diagram of the arrangement of data in the memory shown in Fig. 4. 7V is a No. 48 waveform diagram.

Claims (1)

[Claims] a storage means for storing a plurality of day of the week information and time information corresponding to the plurality of day of the week information; a comparison means for comparing the time information stored in the storage means with predetermined time information; An electronic device characterized by an actuating means actuated by a comparison output, and subsequent operations of the actuating means being sequentially and repeatedly executed in accordance with a plurality of days of the week information stored in the storage means.