JPS6178434U - - Google Patents

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Publication number
JPS6178434U
JPS6178434U JP16459284U JP16459284U JPS6178434U JP S6178434 U JPS6178434 U JP S6178434U JP 16459284 U JP16459284 U JP 16459284U JP 16459284 U JP16459284 U JP 16459284U JP S6178434 U JPS6178434 U JP S6178434U
Authority
JP
Japan
Prior art keywords
oscillators
pair
circuit
frequency
polarity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16459284U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP16459284U priority Critical patent/JPS6178434U/ja
Publication of JPS6178434U publication Critical patent/JPS6178434U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を説明するための
接続図、第2図は第1図の動作を説明するための
波形図、第3図はこの考案の他の実施例を説明す
るためのブロツク図、第4図は従来の周波数逓倍
回路を説明するためのブロツク図である。 11:信号源、12,13:発振器、14:発
振器の出力を加え合せて取出す回路。
Figure 1 is a connection diagram for explaining one embodiment of this invention, Figure 2 is a waveform diagram for explaining the operation of Figure 1, and Figure 3 is for explaining another embodiment of this invention. FIG. 4 is a block diagram for explaining a conventional frequency multiplier circuit. 11: signal source, 12, 13: oscillator, 14: circuit that adds and extracts the outputs of the oscillators.

Claims (1)

【実用新案登録請求の範囲】 A 与えられる論理信号の極性に応じて予め決め
られた位相からN倍の周波数(Nは1以上の正の
整数)で発振を開始する一対の発振器と、 B この一対の発振器に互に極性が逆極性の論理
信号を与え一対の発振器を交互に発振させる信号
源と、 C 上記一対の発振器の出力を加え合せて取出す
回路と、 から成る周波数逓倍回路。
[Claims for Utility Model Registration] A: A pair of oscillators that start oscillating at a frequency N times higher than a predetermined phase according to the polarity of an applied logic signal (N is a positive integer of 1 or more), and B: A frequency multiplier circuit comprising: a signal source that supplies logical signals of opposite polarity to a pair of oscillators to cause the pair of oscillators to oscillate alternately; and a circuit that adds and extracts the outputs of the pair of oscillators.
JP16459284U 1984-10-29 1984-10-29 Pending JPS6178434U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16459284U JPS6178434U (en) 1984-10-29 1984-10-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16459284U JPS6178434U (en) 1984-10-29 1984-10-29

Publications (1)

Publication Number Publication Date
JPS6178434U true JPS6178434U (en) 1986-05-26

Family

ID=30722450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16459284U Pending JPS6178434U (en) 1984-10-29 1984-10-29

Country Status (1)

Country Link
JP (1) JPS6178434U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124164A (en) * 1974-08-21 1976-02-26 Yokogawa Electric Works Ltd SHUHASUTEIBAIKI

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5124164A (en) * 1974-08-21 1976-02-26 Yokogawa Electric Works Ltd SHUHASUTEIBAIKI

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