JPS6177983A - Picture information processing system - Google Patents

Abstract

PURPOSE:To store processed picture data in a CRT display memory and displaying the picture data on a CRT screen at a high speed, by enlarging or reducing pictures with a converting magnification ratio corresponding to the input picture data and the resolution of an output device. CONSTITUTION:A picture reader R is connected to an arithmetic processing system A of a picture information processing system, and the interruption signal given from the reader R is detected by a microprocessor unit MPU via a picture reader interface circuit RIF and a data BUS. Then a DMAC is activated to set the converting magnification data, etc. to a register for control of an enlargement/reduction arithmetic circuit BMP. Thus the BMP is started. Then the RIF is started and the prescribed read picture data of a prescribed size given from the reader R is written to a buffer memory under the control of the DMAC, BMF and RIF. Then the enlargement or reduction processing is carried out by the BMP in response to the resolution of the picture data given from a main memory MM and the picture data given from the reader R. Thus the picture data is displayed on the CRT screen at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a stroke count information processing system for processing stroke count information at high speed.

[Prior art]

In recent years, with the rapid development of image information processing systems centering on Seiko calculation +1k, there is an increasing need to process image information at high speed, for example, from data processing or word processing.

Along with this, image information is taken in from an input device such as an image reading device or an image storage device such as an electronic file, and the image information in 11ii above is processed using an arithmetic processing bag (PED) and sent to an output device such as a laser beam pulling device. i 492 Recorded information is often obtained by sending information @.

In such a case, conventionally, image data read from an image reading device, an electronic file, etc. is stored as one original image data in the main memory C1 of the arithmetic processing device via an interface circuit. After that, the original image data
When displaying on the RT 1tlli surface, the arithmetic processing unit performs arithmetic processing to reduce or enlarge the image, stores the processed image in the T display memory, reads the data from the display memory, and displays it on the ORT. After step 7, perform editing operations such as cropping the image and moving g/j on the C)t screen as necessary.

The edited image drop data μ is stored in a storage device such as an electronic file device or a disk device, or sent to a hard copy device such as a laser printer and recorded therein.

In this 5, the dissolving power of the image reading device 11 is set to 8pe.
l, O) is also 1゛If the resolution of the display device ρ is 74 pels and the resolution of the laser beam printer is 8 pels, then when displaying the image data taken from the image reading device on the CRT screen, the I/ Therefore, in such a case, it was possible to carry out the stone d small processing by having only one reduction processing means with a conversion magnification of 1-i1/2.

However, in recent years, 12pcl, 16pe
1st prize, various high resolution image processing '44jf (
has been realized, and the uui image data read using multiple image processing devices with different resolutions i′ are
1 also l' Self-weight 1 weight g - @ Le Q together It, C) L
't It is necessary to perform reduction processing on the image data to be stored in the NoriFreso/Umemory at the conversion magnification of Tsuta/3.1/4to.

〔the purpose〕

In view of the above points, the present invention provides a ++III image information processing system that can perform high-speed enlargement and f-1 reduction processing using image data and a conversion signal according to the resolution of the output device. is intended to provide.

〔Example〕

An embodiment of the present invention will be described below based on the drawings. In this embodiment, image data is stored in the main memory of the arithmetic processing unit, and at the same time, the arithmetic processing unit of the arithmetic processing unit converts the original image data at a conversion magnification according to the input image data and the resolution of the output device. By performing enlargement or reduction processing and storing the processed image data in, for example, a CRT display memory, image data can be displayed at high speed on both sides of a CRT.

FIG. 1 is a system block diagram of one embodiment according to the present invention. The RFi image reading device, PIF, is the image reading device interface circuit of the arithmetic processing system A, MMt-1,
Main memory, DMACd, direct memory access control circuit, MPLj is a microprocessor writing unit, CF (TI-t, cathode ray tube display, C) (TC is a control circuit of the above CRT, and BMP is a control circuit of the above CRT) A part of the circuit is an arithmetic circuit for enlarging or reducing image data to the display memory of the CRT control circuit.

FIG. 2 is a flowchart showing an example of the operation of the block diagram in FIG.
Executed by U. First, in step 1, the microprocessor assembly unit MPIJU shown in FIG.
When an interrupt signal from the direct memory access control circuit M D is detected, in step 2, control data for controlling the direct memory access control circuit DMAC is set in a register,
M A □.

The DMAC is activated by instructing that it is a direct memory access burst transfer. Precisely in step 3, +if control data such as conversion magnification data for controlling the circuit BMP is set in a register, and this circuit 8MP is activated. Next, in step 4, control data for controlling the interface circuit RIF is set in a register and activated. Next, the task, in step 5, causes the microprocessor unit MPU to
From there, move on to each of the DMAC, BMP, and PIF circuits, and 8
The 11th circuit stores an image (9, f) read at a predetermined resolution of a document of a predetermined size sent from the image reading device R into the rough memory of the 811 circuit. The memory can store one line of image data.In step 6, the image data written to the backup memory of the 811 circuit is stored as data BU.
Output on S. Then, in step 7, data BU
At the same time, the image data sent out on the f-ta BUS is transferred to the main memory MM for 1 tFs under the control of the DMAC circuit.
The 1J sys data is taken into the 51-way BMP circuit, processed by the enlargement or reduction processing circuit (density conversion circuit) in this BMP circuit, and the processed artist data is diluted into the CRT display memory in the CRrC circuit. -MMP1gl path is performed by thinning out 1+l+i elements in the line at the thinning point of the line of image data of BLJS soil, for example! 7
1i114! The image is enlarged by performing line interpolation or pixel interpolation within the line.

Therefore, in step 8; ψ1 It is determined whether or not the exit of the image data from the image reading device R has been completed by detecting the reading device RF (the fall of the enable signal from the image reading device R), and the exit of the image data is Steps 5.6.7 can be repeated until the sending is finished.

Figure 3 shows step 6 in the 70-chart of Figure 2.
．． 7 details rHj) Shows the 7o-chart of the example. F(
After loading the image data sent from the image reading device #R into the buffer memory, the IF circuit sends the F(EQD signal (step 15) 1. On the other hand, the DMAC circuit receives the activation status +, IJK, etc.). and is in a wait state until the REQ signal is detected (step 23).
. RE sent out from the above DMAC circuit branch and PIF circuit
When the Q signal is detected, it sends a signal to the RAC (step 24).

On the other hand, after sending the REQ signal, the RIF circuit holds fpf4Th in a wait state until the RACK signal is completely detected (step 16).
When a signal is detected on C, the data in the buffer memory of RIF[glg is sent out onto the data BUS.Step 17
), send out the data strobe signal DS (step 1
8). On the other hand, the DMAC circuit is in a wait state until the DS signal is detected (step 25), and when the DS signal is detected, it writes the image data on the data BLIS to the main memory MM (step 26), and at the same time writes the image data on the data BLIS to the main memory MM (step 26). Signal DTACK'5r: Send (step 2
7). data transformer 7 account T, C
decrements the counter of (step 28) T,
It is determined whether C is O (step 29).

If T and C are not O, return to the initial state and return to T.

If C is 0, an E N D signal is output and the task of writing is completed (step 30). Hey, this data transfer counter T, the value corresponding to 1 page of Crcu current sword picture 1y data is written into S1. .

Also, it is in a wait state until a signal is detected on the RI Figl path 1-1DTAc (step 19), and υTA
When a signal is detected at L)S, the sending amount of the S signal is stopped (step 20). If the END signal is not detected (step 21), repeat the operation from step 16, and if the END signal is detected (step 21).
(Stop sending the EQD signal (step 22).

Further, the BMP circuit has a D
It remains in a wait state until the S signal is detected (step 10), and when the DS signal is detected, the image data i on the data BUS sent from the RIF circuit is loaded into the input buffer of the BMP circuit (step 11). . This 1iljl data written into the input buffer is
1 has been written in the 41 control register of the BMPlo circuit in advance; the expansion or l' is changed to the reduction circuit and 1 by the h11 law signal.
The ratio is selected and converted (pixel density) to the enlarged or reduced butterfly image data and written to the output buffer of the BMPlol path (step 12). The processed image data written in the actuput buffer l'C of the 8MP circuit is written to a predetermined address of the CRT display memory of the circuit CRTC based on the address data generated by the 8MP circuit (step +3). ), the processed image data is C
It can be displayed completely on the R7 screen. , (-) to judge the END signal. Step 14). END (If No. 1 is not detected, the operation from step 10 is repeated, and when the END signal is detected, operation a is ended.

Note that the processing of the 7C image data shown in FIG.
This is performed every time 16 bits of image data is output from the RIF circuit. Therefore, the image data read by the image reading device R'''C is transferred to the main memory MM to the arithmetic processing system.
At the same time that Kt'f is input, a processed image obtained by processing the original image is displayed on the CR7 screen, so that the above-mentioned demand for high-speed processing can be met.

FIG. 4 is a diagram L21 showing an overview of the BMP regeneration.
t' In Figure 11, BT is a path transceiver for transmitting data on BO3 in an appropriate manner,
R) (holding the decomposition η values of the input device and output device in 2
A magnification change safe register, DEC has developed a CRI (I
A decoder for selecting an appropriate magnification/reduction process from the stored resolution. ) CON1 to CON3 are enlargement/reduction processing circuits for converting the pixel density fr of input image data, INB is an input buffer for storing one line of input image data, and CUTBF is a pixel density conversion formula. This is an actuate buffer for storing one image data tl lines. 2. Degradation of the reading device and output device is applied during communication between the arithmetic processing system and the reading device and output device.

First, as shown in step 3 in Figure 42, the conversion magnification data (separation of input device and output device 1'?) is
The MPU sets the variable ratio save register CRRK from 8US in FIG. 4 via the path transceiver 8Ti. According to the value of the magnification conversion data set in this CRRK, 3 is output from the decoder DEC.
One of the two enable signals is selected. Therefore, the enlargement/reduction processing circuits DCO+XJ1 and DCON2
, one of DCOIN 3 is operational I! ! ,!
! :Next, when the processing operation becomes as shown in Fig. 3, the image data is sent from the RIF circuit to BO3 in the fourth stage, and the image data is stored in the input buffer INB via the path transceiver 8Tr. It will be done. The stored image is enlarged or reduced by one of the enlargement/reduction processing circuits DCON1 to DCON3 selected according to the magnification conversion data and is stored in the actuate buffer 0UTB. In this first embodiment, there are three ri enlargement/reduction processing circuits, but of course, the more the number of ri enlargement/reduction processing circuits, the more input/output devices/reduction processing circuits with different resolutions.
Compatible with lK.

The enlargement/reduction processing circuit within the Rizani8M8 circuit will be explained.

FIG. 5 is an example of an enlargement/reduction processing circuit in the 8M8 circuit, which performs enlargement or reduction processing of input binary image data based on control data output from the MPU. In SI, a1 on each line represents the number of bits of the program drop data. Here, 20 is a BUS driver/receiver that manages the input/output of image data, 21, 26, and 28 are latch circuits, and a predetermined Villato selector from among the 16-bit image data is selected according to the output from the 22μ address generator z3. 23 is an address generator that generates an address according to a set magnification, and 24 is a control that controls the address generation mode of the address generator 23 based on a control command (magnification, etc.) output from the MPU. A circuit, a serial/parallel converter that converts the 1-bit music image data serially output from the 25-bit data selector into 16-bit parallel image data, This is a buffer memory that stores lines. To explain, 16-bit image data input via the BUS driver/receiver 20 is stored in the data selector 22 via the latch 21. The address generator 23 generates an address according to the set magnification, and the address generator 23 generates an address according to the set magnification.
When the magnification of
, 6, 8, 1 (1, 12, 14 addresses are selected in sequence. As a result, each bit is thinned out I!
Bit-reduced image data is sequentially input to a serial/parallel converter. Serial/parallel converter 25 is 16
Since up to two bits can be stored, when the next 8-bit reduced image data to be output is input from the data selector 22, the parallel 16-bit reduced image data is stored in the latch 2.
6) (output to AM21. Then, lunch 28,
The data is stored in the CRT display memory via the BLJS driver/receiver 20. Further, when a magnification of 2.0 is set by a control command from the MPU, each address of the address generator 23f'i data selector is specified twice. As a result, the enlarged -1 image data in which the d bits have been enlarged by .delta. are sequentially input to the serial/parallel converter. Note that the 16-bit (1 word) image data stored in the data selector 22 becomes 32 points by specifying each address twice, so the data is sent to the serial/parallel converter 25 twice. Enlarged image data will be input separately. Then, the enlarged 1If output from the serial/parallel converter 25
The i-image data is stored in the RAM 27 as described above.
R,T display memo IJK@deposited. The above-mentioned enlargement/reduction processing is performed in the row direction (main scanning direction), and the enlargement/reduction processing in the column direction is performed as follows.

For example, when a magnification of 0.5 is set, the 8 to 12 circuits output the small image data stored in the RAM2γ every other line.As a result, the lines are thinned out by 1/2 in the column direction. If a magnification of 2.0 is set, the image data reduced to
One line of enlarged image data f stored in the P circuit dRAM 21: Repeatedly output twice. As a result, image data enlarged twice in the column direction is output from the RAM 27.

As explained above, the image data read by the image reading device OIR is written to the main memory MM of the arithmetic processing unit jtA in real time, and the original image data is enlarged or reduced at a predetermined magnification. CR is a poorly processed image.
The data is written to the T display memory and displayed on the CRT screen.

Further, when the RIF circuit detects the END signal, it stops sending the REQ signal.

In this example, the image data is the main memo IJM.
At the same time as it is written to M, it is processed and stored in the memory for OR and T display, but main memo 17 MM, C! RT
Instead of storing it in the display memory, it may be sent to the first and second printers.

Also, where is the image data? 1! The operation is not limited to enlarging/reducing processing (density conversion processing), but may be other processing such as trimming, masking, rotation, etc.

[Song example]

In the embodiment described above, the source image data is image data read by an image reading device, but it may be image data that has been stored in advance in a storage device such as an electronic file device.

Further, the source image data may be image data mediated by a line such as a local area network.

Moreover, in the above embodiment, the source data is
The explanation was given as III'izuka data, but in advance the ROM
The font data may be character font data stored in a storage means such as a storage device or a storage device.

In either case, according to these embodiments, the image reading device? ? The image data read by R, etc. is transferred to the main memory MM of the arithmetic processing unit itA in real time, and the original image data is enlarged at a predetermined magnification, and the slightly distorted processed image is displayed on the CRT. (Effect) As explained above, according to the present invention, the image 19
Since the data is configured to be enlarged or reduced by a conversion signal corresponding to the image data and the decomposition of the output device, it is possible to display the processed image data on the screen of the display device at high speed.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram of an embodiment of the present invention, FIG. 2 is an operation flowchart thereof, FIG. 3 is a detailed flowchart of FIG. 2, and FIG. 4 is a schematic block diagram of BPM@road. FIG. 5 is a block diagram showing 1fllt of the enlargement/reduction processing circuit of the A4 BPM circuit. R... Image reading device F/ (image information generating device) A...... Arithmetic processing system PIF...
・・Picture r8+reading device interface circuit MM・・・・・ Main memory (first storage means)
DMAC... Direct memory access control circuit MPU... Microgross unit C)
(T...Cathode ray tube CRTC...l"I upper CRT control circuit BMP
......Enlargement/reduction calculation circuit 8US...Data bus BT...Pastra 7 Seaver CRR...
...Magnification conversion save register DEC...Decoder DCON...Enlargement/reduction processing apposition 1, 2.31NB.
...Implant sofa QUTB...attogutsutono (sofa drawing child, '', 2': further; shi) Figure 7〒 L --- 1 --- 11 (13204
-P) -f Successor fj Official Book 1 Recitation October 3, 1959 Manabu Shiga, Commissioner of the Patent Office, Patent Application 2 filed on September 25, 1980, Title of Invention Image Information Processing System 3, Amendment Relationship to this case Applicant name C100) Canon Co., Ltd. Tamuracho Building (full text, all drawings) 1/, 7″

Claims (1)

[Claims] Image information processing in which image information is stored in a first storage means of the arithmetic processing system, and at the same time, the image information is subjected to predetermined processing in the arithmetic processing system and then stored in a second storage means of the arithmetic processing system. In the system, an output means for outputting image information, a plurality of enlargement/reduction processing means for enlarging or reducing the image information, and the arithmetic processing system,
a first giving means for giving a resolution value of the input image data; a second giving means for giving a resolution value of the output means; an image processing system comprising a selection means for selecting one of the enlargement/reduction processing means.