JPS6177358A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS6177358A JPS6177358A JP59198839A JP19883984A JPS6177358A JP S6177358 A JPS6177358 A JP S6177358A JP 59198839 A JP59198839 A JP 59198839A JP 19883984 A JP19883984 A JP 19883984A JP S6177358 A JPS6177358 A JP S6177358A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- pat
- electrical connection
- polycrystalline
- adhered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は導電層の溶断の有無により情報を記憶する続出
専用メモリ、所謂フユーズＲＯＭの構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of a so-called fuse ROM, a read-only memory that stores information depending on whether or not a conductive layer is fused.
フユーズＲＯＭは、プログラマブルＲＯＭの１種で、集
積回路（ＩＣ）の製造に使うフォトマスクに情報を固定
したマスクＲＯＭに比べ、ユーザが簡易にプログラムで
きるため、装置の開発段階等で広く利用されている。Fuse ROM is a type of programmable ROM, and compared to mask ROM, which has information fixed on a photomask used in integrated circuit (IC) manufacturing, it can be easily programmed by the user, so it is widely used in the development stage of equipment. There is.
第４図は従来例によるフユーズＲＯＭの平面図である。 FIG. 4 is a plan view of a fuse ROM according to a conventional example.
図において、基板上に形成された絶縁層上に厚さ２００
０〜５０００人の多結晶珪素層を被着し、パターニング
して熔融部３八と電気接続部３Ｂを形成する。In the figure, the insulating layer formed on the substrate has a thickness of 200 mm.
A layer of 0-5000 polycrystalline silicon is deposited and patterned to form fused portions 38 and electrical connections 3B.
−電気接続部３Ｂに電気取出部３Ｃを設ける。- An electrical connection section 3B is provided with an electrical outlet section 3C.
熔融部３Ａの幅は、パターニングの精度上最小で１μｍ
程度で、従って熔融部３Ａの断面積は、（２０００〜５
０００人） Ｘ１００ＯＯÅ以上となる。The width of the melted part 3A is at least 1 μm for patterning accuracy.
Therefore, the cross-sectional area of the melting part 3A is (2000 to 5
000 people) X100OOÅ or more.
従来のフユーズＲＯＭにおいては、微細化が難しく、従
って書込のための溶断に高電力を必要とし、高集積化、
高信転化が困難であった。Conventional fuse ROMs are difficult to miniaturize, and therefore require high power to fuse for writing.
It was difficult to convert to high confidence.
上記問題点の解決は、基板上に形成された絶縁層の段差
部に被着された導電層を有し、該導電層の断続により情
報を記憶する本発明による半導体記憶装置により達成さ
れる。The above problems are solved by a semiconductor memory device according to the present invention, which has a conductive layer deposited on the stepped portion of an insulating layer formed on a substrate, and stores information by discontinuing the conductive layer.
第１図（ａｌ、 （ｂｌはそれぞれ本発明によるフユー
ズＲＯＭの平面図と熔融部の断面図である。FIG. 1 (al) and (bl) are a plan view and a sectional view of a fuse ROM according to the present invention, respectively.
第１図（ａ）において、基板上に形成された絶縁層の段
差上に厚さ２０００〜５０００人の多結晶珪素層を被着
し、パターニングして熔融部３Ａと電気接続部３Ｂを形
成する。熔融部３Ａは段差部にのみ多結晶珪素層が残る
ようにする。In FIG. 1(a), a polycrystalline silicon layer with a thickness of 2,000 to 5,000 layers is deposited on the step of the insulating layer formed on the substrate and patterned to form a melted part 3A and an electrical connection part 3B. . In the melted part 3A, the polycrystalline silicon layer remains only in the step part.
電気接続部３Ｂに電気取出部３Ｃを設ける。An electrical connection section 3B is provided with an electrical outlet section 3C.
この場合、熔融部３Ａの断面積は、
（２０００〜５０００人）Ｘ （２０００〜５０００人
’） Ｘ （１／２） 人となり、従来例の１７４〜
１／１０となる。In this case, the cross-sectional area of the melting section 3A is (2000-5000 people) x (2000-5000 people') x (1/2) people, which is 174 -
It becomes 1/10.
第２図（ａ）、（ト）ｌ、 （Ｃ１は熔融部を製造工程
順に示す断面図、（ｄ）は電気接続部の断面図である。2(a), (g)l, (C1 is a cross-sectional view showing the melting part in the order of manufacturing steps, and (d) is a cross-sectional view of the electrical connection part.
第２図（ａ）において、基板１の上に第１の絶縁層とし
て熱酸化による二酸化珪素（ＳｉＯｚ）層２を被着し、
２０００人の段差を設ける。In FIG. 2(a), a silicon dioxide (SiOz) layer 2 is deposited as a first insulating layer on a substrate 1 by thermal oxidation,
There will be a gap of 2,000 people.
第２図０１）において、段差を覆って厚さ２０００人の
多結晶珪素層３を被着する。In FIG. 2 01), a polycrystalline silicon layer 3 having a thickness of 2000 wafers is deposited over the step.
多結晶珪素層３の被着は、化学気相成長（ＣＶＤ）法を
用い、０．２〜Ｉ Ｔｏｒｒに減圧して、８００℃でモ
ノシラン（Ｓ ｉ Ｈａ）を熱分解して行う。The polycrystalline silicon layer 3 is deposited using chemical vapor deposition (CVD) by thermally decomposing monosilane (S i Ha) at 800° C. under reduced pressure from 0.2 to I Torr.
第２ 図（Ｃ）において、パターニングして熔融部３Ａ
を形成する。In FIG. 2 (C), patterning is performed to melt the melted part 3A.
form.
パターニングはりアクティブ・イオン・エツチング（Ｒ
ＩＥ）により、エツチングガスとして四塩化炭素（ＣＣ
１４）を用い０．５Ｔｏｒｒに減圧して、周波数１３．
５６ＭＩＩＺの電力３００Ｗを印加して異方性エツチン
グを行う。Patterning beam active ion etching (R
IE), carbon tetrachloride (CC) was used as an etching gas.
14) to reduce the pressure to 0.5 Torr and set the frequency to 13.
Anisotropic etching is performed by applying a power of 300 W of 56 MIIZ.
第２図（（ｆ）において、パターニングして電気接続部
３Ｂを形成し、その上に第２の絶縁層としてＣＶＤによ
るＳｉｎ２層４を被着し、電気取出部３Ｃを開口する。In FIG. 2(f), an electrical connection part 3B is formed by patterning, and a CVD Sin2 layer 4 is deposited thereon as a second insulating layer, and an electrical lead-out part 3C is opened.
Ｓｉｎ、層（７）ＣＶＤ条件は、ＳｉＨ４と酸素（０□
）を用いて０．５Ｔｏｒｒ、 ４２５℃で行う。Sin, layer (7) CVD conditions are SiH4 and oxygen (0□
) at 0.5 Torr and 425°C.
第３図（ａｌ、 （ｂｌ、 （Ｃ１はそれぞれ本発明に
よる積層構造のフユーズＲＯＭの平面図と、第１熔融部
の断面図と、第２熔融部の断面図である。FIGS. 3 (al, bl, (C1) are a plan view, a cross-sectional view of the first melting part, and a cross-sectional view of the second melting part, respectively, of a fuse ROM having a laminated structure according to the present invention.
第３図＋ａｌにおいて、基板上に形成された第１の絶縁
層の段差上に厚さ２０００〜５０００人の第１の多結晶
珪素層を被着し、パターニングして第１の熔融部３Ａと
第１の電気接続部３Ｂを形成する。第１の熔融部３＾は
段差部にのみ多結晶珪素層が残るようにする。In FIG. 3+al, a first polycrystalline silicon layer with a thickness of 2,000 to 5,000 layers is deposited on the step of the first insulating layer formed on the substrate, and patterned to form a first melted part 3A. A first electrical connection 3B is formed. In the first melted part 3^, the polycrystalline silicon layer remains only in the stepped part.
第１の電気接続部３Ｂに第１の電気取出部３Ｃを設ける
。A first electrical connection section 3B is provided with a first electrical extraction section 3C.
さらにその上に第２の絶縁層を被着し、第２の絶縁層の
段差を覆って厚さ２０００〜５０００人の第２の多結晶
珪素層を被着し、パターニングして第２の熔融部５Ａと
第２の電気接続部５Ｂを形成する。第２の熔融部５Ａは
段差部にのみ多結晶珪素層が残るようにする。Furthermore, a second insulating layer is deposited thereon, and a second polycrystalline silicon layer with a thickness of 2,000 to 5,000 is deposited to cover the steps of the second insulating layer, patterned, and a second polycrystalline silicon layer is deposited to cover the steps of the second insulating layer. A portion 5A and a second electrical connection portion 5B are formed. In the second melted portion 5A, the polycrystalline silicon layer remains only at the step portion.
第２の電気接続部５Ｂに第２の電気取出部５Ｃを設ける
。A second electrical connection section 5B is provided with a second electrical connection section 5C.
第３図（ｂ）はＡ−Ａ断面図、第３図（Ｃ）はＢ−Ｂ断
面図である。FIG. 3(b) is a sectional view taken along the line AA, and FIG. 3(C) is a sectional view taken along the line BB.
基板１の上に第１の絶縁層として熱酸化によるＳｉ０２
層２を被着し、２０００人の段差を設ける。Si02 is deposited as a first insulating layer on the substrate 1 by thermal oxidation.
Layer 2 is applied and a step of 2000 is provided.
つぎに段差を覆って厚さ２０００人の第１の多結晶珪素
層３を被着する。A first polycrystalline silicon layer 3 having a thickness of 2000 layers is then applied over the steps.
つぎにパターニングして第１の熔融部３Ａ、第１の電気
接続部３Ｂを形成し、その上に第２の絶縁層としてＣＶ
ＤによるＳｉｎ、層４を被着し、第１０電気取出部３Ｃ
を開口する。Next, patterning is performed to form a first melting part 3A and a first electrical connection part 3B, and a CVV is formed as a second insulating layer thereon.
D by Sin, layer 4 is deposited, and the 10th electrical outlet part 3C
Open.
つぎに第２の絶縁層４の段差を覆ってＩさ２０００人の
第２の多結晶珪素層５を被着する。A second polycrystalline silicon layer 5 of 2,000 layers is then deposited over the step of the second insulating layer 4.
つぎにパターニングして第２の熔融部５八、第２の電気
接続部５Ｂを形成し、その上に第３の絶縁層としてＣＶ
ＤによるＳｉ０２層６を被着し、第２の電気取出部５Ｃ
を開口する。Next, patterning is performed to form a second melted part 58 and a second electrical connection part 5B, and a third insulating layer is formed on the CV
A Si02 layer 6 is deposited by D, and the second electrical lead-out portion 5C is formed.
Open.
配線層７，８はアルミニウム（Ａ１）を蒸着して形成す
る。The wiring layers 7 and 8 are formed by vapor depositing aluminum (A1).
この積層構造は原理的には何層でも形成可能である。In principle, this laminated structure can be formed with any number of layers.
以上詳細に説明したように本発明によれば、フユーズＲ
ＯＭにおいては、微細化が可能となり、従って書込のた
めの溶断電力を低減し、高集積化、高信頼化に寄与でき
る。As explained in detail above, according to the present invention, fuse R
In OM, it becomes possible to miniaturize the device, thereby reducing the fusing power for writing and contributing to higher integration and higher reliability.
第１図１８１． （ｂ）はそれぞれ本発明によるフユー
ズＲＯＭの平面図と熔融部の断面図、
第２図＋ａ）、 （ｂ）、 （Ｃ）は熔融部を製造工程
順に示す断面図、＋ｄ＋は電気接続部の断面図、第３図
（ａｌ、 （ｂ）、 （Ｃ１はそれぞれ本発明による積
層構造のフユーズＲＯＭの平面図と、第１熔融部の断面
図と、第２熔融部の断面図、
第４図は従来例によるフユーズＲＯＭの平面図である。
図において、
１は基板、
２は第１の絶縁層（ＳｉＣｈ層）、
３は第１の多結晶珪素層、
３＾は第１の熔融部、
３Ｂは第１の電気接続部、
３Ｃは第１の電気取出部、
４は第２の絶縁層（ＣＶ ＤＳｉ（ｈ層）、５は第２の
多結晶珪素層、
５Ａは第２の熔融部、
５Ｂは第２の電気接続部、
５Ｃは第２の電気取出部、
６は第３の絶５ｔｉｌｌ （ＣＶ Ｄ Ｓｉ０ｇ層）、
７．８は配線層（Ａｔ層）
を示す。
昇３図
第４図
Ｂ−Ｂ訴面Figure 1 181. (b) is a plan view and a sectional view of the melting part of the fuse ROM according to the present invention, Figure 2 +a), (b), and (C) are sectional views showing the melting part in the order of manufacturing steps, +d+ is the electrical connection part. (C1 is a plan view of a fuse ROM having a laminated structure according to the present invention, a cross-sectional view of the first melting part, a cross-sectional view of the second melting part, and FIG. 4, respectively. is a plan view of a fuse ROM according to a conventional example. In the figure, 1 is a substrate, 2 is a first insulating layer (SiCh layer), 3 is a first polycrystalline silicon layer, 3^ is a first melting part, 3B is the first electrical connection part, 3C is the first electricity extraction part, 4 is the second insulating layer (CV DSi (h layer)), 5 is the second polycrystalline silicon layer, 5A is the second melting part , 5B is the second electrical connection part, 5C is the second electricity extraction part, 6 is the third isolation part (CVD Si0g layer),
7.8 indicates the wiring layer (At layer). Figure 3 Figure 4 B-B Complaint
Claims (1)
層を有し、該導電層の断続により情報を記憶することを
特徴とする半導体記憶装置。A semiconductor memory device comprising a conductive layer deposited on a stepped portion of an insulating layer formed on a substrate, and storing information by discontinuing the conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198839A JPS6177358A (en) | 1984-09-21 | 1984-09-21 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59198839A JPS6177358A (en) | 1984-09-21 | 1984-09-21 | Semiconductor memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6177358A true JPS6177358A (en) | 1986-04-19 |
Family
ID=16397771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59198839A Pending JPS6177358A (en) | 1984-09-21 | 1984-09-21 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6177358A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63140550A (en) * | 1986-12-01 | 1988-06-13 | Mitsubishi Electric Corp | Elecric fuse for redundant circuit |
| JP2004266165A (en) * | 2003-03-03 | 2004-09-24 | Sharp Corp | Nonvolatile memory element, nonvolatile memory circuit, nonvolatile memory card, and recorder/reproducer |
-
1984
- 1984-09-21 JP JP59198839A patent/JPS6177358A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63140550A (en) * | 1986-12-01 | 1988-06-13 | Mitsubishi Electric Corp | Elecric fuse for redundant circuit |
| JP2004266165A (en) * | 2003-03-03 | 2004-09-24 | Sharp Corp | Nonvolatile memory element, nonvolatile memory circuit, nonvolatile memory card, and recorder/reproducer |
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