JPS6177192A - Decoder circuit - Google Patents

Abstract

PURPOSE:To lower a rate of a consumed power of a decoder circuit occupying a consumed power of a whole chip by setting a circuit condition having no consumption of power by a level setting of a selecting signal. CONSTITUTION:The titled circuit is constituted of MOST groups 7 having Ao-An address signal groups 6 connected to respective gates of plural MOS transistors MOST, a NOR circuit 2 comprising of a MOSTQ1 and a MOSTQ2 connected to a signal line 8 having a gate to which a selecting signal S1 is impressed, an inverter 3 comprising a MOSTQ3, a MOSTQ4 and a MOSTQ5 having a gate connected to the signal line 8, and a push-pull type buffer 4 comprising of a MOSTQ6 and a MOSTQ7 having a drain connected to a signal line 9 to which selecting signal S2 is impressed, and connected to an output terminal 5 connected to a word line. Thereby, when inputting a chip enable signal as the selecting signals S1, S2, the consumed power of a decoder circuit can be zero during a chip being not selected.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a decoder circuit comprised of insulated gate field effect transistors.

Conventional configuration and its problems A memory device such as a ROM requires a decoder circuit for selecting one of a plurality of word lines. Generally, a plurality of address signals are input to a NOR circuit, and the output of the NOR circuit is passed through a buffer to drive a word line.

Figure 1 is a circuit diagram showing the configuration of a conventional decoder circuit, in which a plurality of address signal groups 1 are input.
A MOS type NOR circuit 2, an E/D MOS type inverter 3 to which the output of this NOR circuit is applied as an input, and an output of the NOR circuit 2 are connected to the gate of a MOS transistor on the power supply side. The output of the E/D MOS type inverter 3 is connected to the gate of a ground-side MOS transistor. Note that the output terminal 5 of the Phnom Yupur type buffer 4 is a word line (not shown).
When connected to 7, only the word line connected to the decoder circuit including the NOR circuit in which all address inputs become low level is precharged and becomes high level, resulting in a selected state.

Incidentally, a problem with the decoder circuit having such a configuration is the problem of power consumption. That is,
When the decoder circuit shown in Figure 1 is used, the number of decoder circuits equal to the number of word lines is required1, which is 64KRO.
If M has a decoder circuit of the conventional configuration, the number of decoder circuits will be 266, which is the same number as the number of word lines. The power consumption of these 256 decoder circuits accounts for about 60% of the power consumption of the entire 64K ROM chip. Therefore, the amount of increase in power consumption in the decoder circuit section becomes more significant than the amount of increase in power consumption in the peripheral circuits. As described above, it has been difficult to reduce the power consumption of the entire chip by using a decoder circuit with a conventional configuration.

Object of the Invention The object of the present invention is to provide a decoder circuit in a large-capacity memory device having a circuit configuration that reduces the proportion of power consumption of the decoder circuit in the power consumption of the entire chip. The decoder circuit of the invention includes a MIS transistor/dimetal group consisting of a plurality of insulated gate field effect transistors (M-S transistors) whose sources are grounded, whose drains are commonly connected, and whose gates are connected to an address signal line. , a first MIS transistor whose drain is connected to the power supply line, and whose gate and source are commonly connected; a second MI to which the source circuit is connected and the first selection signal is applied to the gate;
a third MIS transistor whose gate and source are commonly connected; a fourth MIS transistor whose gate is connected to the drain of the second MIS transistor; and a first selected transistor whose gate is connected to the drain of the second MIS transistor. A series connection body of a fifth MISI-run to which a signal is applied is connected between a power supply line and a ground point, and an inverter section and a gate formed by 7 are connected to the drain of the second MISI transistor. a sixth MIS transistor/distor to which a second selection signal is applied, a gate of which is connected to the drain of the fourth MIS transistor;
At t7I? has been completed. According to this configuration, the state of the decoder circuit can be set to either an active state with power consumption or a standby state without power consumption by level control of the first and second selection signals. .

DESCRIPTION OF EMBODIMENTS FIG. 2 is a circuit diagram showing an example of the circuit configuration of a decoder circuit according to the present invention, and the configuration and circuit operation will be described in detail below.

In the decoder circuit of the present invention, the address signal line group 6 A0 to A is connected to each gate of a plurality of MOS transistors, all drains are commonly connected, and each source is connected to a ground point. Transistor/meta Q1 (MOS) whose source is connected to the drain common connection point of the MO3l-transistor group and whose gate is connected to the signal line 8 to which the selection signal S1 is applied.
A NOR circuit is constituted by a MOS transistor Q2 whose gate and source are commonly connected and connected to the drain of the MOS transistor Q1, and whose drain is connected to the power supply line. Mo3 l transistor Q3 connected to the power line,
The same MOS) is connected in series between the gate-source common connection point of transistor Q5 and the ground point, and the gate is
o3) Mo3 connected to the drain of transistor Q1
) Lanozister Q4 and M whose gates are connected to the signal line 8
o3) An inverter is configured with the transistor Q5, and the drain is connected to the signal line 9 to which the selection signal S2 is applied, and the gate is connected to the drain of the MOS transistor Q1.Mo3) The source of the transistor Q6 and the source A push-pull type buffer is constructed by connecting the drains of the MOS transistor Q7, which is connected to the ground point and whose gate is connected to the drain of the transistor Q4, and the output terminal 5 connected to the word line is connected to this common connection point. ing. It should be noted that the MOS transistors Q2 and Q3 constituting this decoder circuit are of the depletion type, and all the other Mo3) transistors are of the enhancement type.

In a memory device incorporating a large number of decoder circuits with such a configuration, in order to eliminate unnecessary power consumption by the decoder circuits, it is necessary to set the selection signals S1 and Sze, which are applied to the decoder circuits not involved in word line selection, to a low level. do. That is, when the selection signal S1 becomes low level, the MOS transistors Q+ and Qs turn off [Jζ state, and the selection signal 82 becomes the power ratio - level, which cuts off the through current of the push-pull type buffer. do. At this time, the output of the Gush pull type buffer is at a low level 9, and the word line is at a low level and in a non-selected state.

Therefore, by inputting the chip enable signal as the selection signals S1 and S2, the power consumption by the decoder circuit can be reduced to zero at the time of chinobu deselection. !
, a set of address signals B, 100 are used as the selection signals S1 and S2, and half of the multiple decoder circuits are provided with the address signal B-i as the selection signal J+"2;
The remaining half of the decoder circuits receive the selection signal S1. When an address signal of 100 is input as S2, half of the decoder circuits are in a standby state that does not consume power during operation, and the power consumption of the entire decoder circuit is half of that when using the two conventional decoder circuits, resulting in lower power consumption. can be achieved.

The present invention has been described above with reference to FIG. 2, but the illustrated decoder circuit is one embodiment of the present invention. For example, the final stage Gino/Nibble type buffer is connected to one decoder circuit with multiple thresholds. Is possible. However, when using such a circuit configuration, the signal applied as the power supply to each Phnom Yuble type buffer must be a signal that always goes to low level when the 1 selection signal S goes to low level and enters the power down mode. There is. Also, change the types of transistors used in this circuit and add circuit functions as necessary! Of course I do.

Effect of the invention 14↓ The decoder circuit of the present invention allows setting of the circuit state without power consumption by setting the level of the selection signal.1.
Therefore, MO3 requires multiple decoder circuits.
By using the decoder circuit of the present invention in an integrated circuit,
It is possible to reduce the power consumption of the MO3 balance circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a conventional decoder circuit, and FIG. 2 is a circuit diagram showing the configuration of the decoder circuit of the present invention. 2...NOR circuit, 3...Inverter, 4
...Gino/nibble type buffer, 5...Output terminal, 6...Address signal line group, 7...
MoS transistor group, 8, 9...Signal line to which a selection signal is applied, Q1-Q,...MOS transistors.

Claims (1)

[Claims] a group of MIS transistors in which the sources of the plurality of MIS transistors are grounded, the drains are commonly connected, and each gate is connected to an address signal line; a first MIS transistor in which the drains are connected to a power supply line and the gates and sources are commonly connected; A drain-source circuit is connected between the gate-source common connection point and the common connection point of the MIS transistor group, and a second transistor whose gate is applied with the first selection signal
a third MIS transistor whose gate and source are commonly connected; a fourth MIS transistor whose gate is connected to the drain of the second MIS transistor; and a fifth MIS transistor to which a first selection signal is applied to the gate. a sixth inverter section formed by connecting a series connection body with the transistor between a power supply line and a ground point; and a sixth inverter section whose gate is connected to the drain of the second MIS transistor, and a second selection signal is applied to the drain.
A push-pull type buffer section consisting of an MIS transistor and a seventh MIS transistor whose gate is connected to the drain of the fourth MIS transistor, whose drain is connected to the source of the sixth MIS transistor, and whose source is connected to the ground point. Features a decoder circuit.