JPS617666A - Nonvolatile semiconductor memory storage - Google Patents

Abstract

PURPOSE:To obtain a stable writing holding stage by forming an unp-doped semiconductor layer having electron affinity smaller than two semiconductor layers, to which secondary electron gas layers are shaped, between these two semiconductor layers. CONSTITUTION:An un-doped GaAs layer 2, an un-doped AlGaAs layer 3, an n type AlGaAs layer 4, an un-doped AlGaAs layer 5, an un-doped GaAs layer 6, an un-doped AlGaAs layer 7, an un-doped GaAs layer 8, an un-doped AlGaAs layer 9, an n type AlGaAs layer 10 and an n type GaAs layer 11 are formed onto a semi-insulating GaAs substrate 1 in succession. Source and drain electrodes 13, 14 brought into ohmic-contact with the layer 6 are shaped, and an opening section 19 is formed between the electrodes 13, 14 and a gate electrode 12 is shaped. According to the constitution, the layer 7 having electron affinity smaller than two-element electron gas layers 15, 16 formed on writing is shaped among the layers 15, 16, thus completely isolating the layers 15, 16 under a floating state after writing, then obtaining stable memorizing operation.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device having a superlattice structure having a plurality of heterojunctions, and relates to a structure in which a stable charge retention state can be obtained after writing.

[Conventional technology]

In recent years, two-dimensional electron gas (2DE) which has a GaAs/n-Aj2GaAs heterostructure and is formed at the hetero interface
The development of high-speed devices that can obtain extremely high electron mobility by using G) layers is progressing, and various configurations have been proposed for nonvolatile semiconductor memory devices that use two-dimensional electron gas layers. ing.

The present applicant proposed this nonvolatile semiconductor memory device in Japanese Patent Application No. 85301/1983 as a structure shown in the cross-sectional view of FIG. 4, which will be explained below.

In the figure, 21 is a semi-insulating GaAs substrate, 22 is an undoped GaAsFit, and 23 is an undoped AlGaAs substrate.
#24 is n-type AlGaAs layer, 25 is undoped An
GaAs layer, 26 is undoped GaAs layer, 27 is n-type GaAsN, '28.29 is n-type with donor impurity introduced.
30 and 31 are source and drain electrodes, 32 is a gate electrode, and 33 and 34 are two-dimensional electron gas layers.

When a positive voltage is applied to the gate electrode 32 of this nonvolatile semiconductor memory device, some of the electrons of the two-dimensional electron gas N33 at the telo interface between the undoped GaAs q 22 and the undoped AlGaAs layer 23 are converted to the undoped A'ffGaA.
s1i23. N-type Ajl! The GaAs1i24 passes through the undoped AlGaAs layer 25 due to the tunnel effect and joins the two-dimensional electron gas 1it34.

When the movement of electrons is completed, a writing state is entered, and the electrons of the two-dimensional electron gas 1it34 are transferred to the undoped GaA3 layer 2.
This state is preserved because it is sandwiched between a potential barrier at the hetero-interface between the gate electrode 6 and the undoped AlGaAs layer 25 and a short barrier formed by the n-type GaAs layer 27 and the gate electrode 32.

To perform erasing to return this state to the original state, a voltage of opposite polarity to that for writing is applied to the gate electrode 32.

This nonvolatile semiconductor memory device uses electrons in the two-dimensional electron gas layer as carriers during reading, and therefore can perform extremely high-speed reading.

[Problem that the invention seeks to solve]

In the write hold state of the nonvolatile semiconductor memory device, 2
The dimensional electron gas 134 and the two-dimensional electron gas layer 33 are undoped Aj! GaAs1i25. n-type A I G a
A s Fit 24 and undoped AlGaAs layer 2
It is electrically isolated by 3. However, the thickness of the undoped A#GaASJii 25 and the undoped AlGaAs layer 23 is extremely thin, and the n-type A# that supplies carriers
Since the electrical conductivity of the GaAs layer 24 is high, complete separation was not performed, and the electrons accumulated in the two-dimensional electron gas IW 34 crossed the barrier of the layer made of A4GaAs and were accumulated in the two-dimensional electron gas layer 34. electron is A4GaAs
This has the drawback that a stable write-holding state cannot be obtained because the electrons may flow to the two-dimensional electron gas layer 33 beyond the barrier of the layer consisting of the above.

[Means for solving problems]

The present invention solves the above-mentioned drawbacks and provides a non-volatile semiconductor memory device that can obtain a stable write retention state without decreasing the electrons stored in the two-dimensional electron gas layer. , a first carrier supply layer and a first and second semiconductor layer forming a channel layer, which are formed in order on a substrate to form a heterojunction, and an undoped semiconductor layer having a lower electron affinity than the second semiconductor layer. a third semiconductor layer, a fourth semiconductor layer having a higher electron affinity than the third semiconductor layer, and a fifth semiconductor layer serving as a second carrier supply layer;
comprising a gate electrode disposed on the fifth semiconductor layer, and two electrodes disposed opposite to each other via the gate electrode and each ohmically connected to the second semiconductor layer. This is done using a non-volatile semiconductor memory device.

[Effect]

In the write state, the nonvolatile semiconductor device has electrical conduction between a fourth semiconductor layer in which a two-dimensional electron gas layer for accumulating electrons is formed, and two electrodes in which a two-dimensional electron gas layer is formed and are ohmically connected. A two-dimensional electron gas is formed in the fourth semiconductor layer by having an undoped third semiconductor layer with a lower electron affinity than the second and fourth semiconductor layers between the second semiconductor layer to be brought into the state. This is intended to completely electrically separate the layer and the two-dimensional electron gas layer formed in the second semiconductor layer.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a sectional view of a nonvolatile semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is a semi-insulating GaAS substrate, 2 is undoped GaAs1iJ, and 3 is undoped AlGaAs.
Layer 4 is n-type Ajl! GaAs layer.

5 is an undoped AlGaAs layer, 5 is an undoped GaA layer
s layer, 7 is undoped Aj2GaAslii, 8 is undoped GaAs layer, 9 is undoped AlGaAs layer, 1
0 is an n-type A6GaAs layer, 41 is an n-type GaAsJit,
12 is a gate electrode, 13 and 14 are source and drain electrodes, and 15 and 16 are two-dimensional electron gas layers.

Data for each of the illustrated semiconductor layers are shown below.

(thickness 75000 for 11 undoped GaAs layer 2
Thickness for (2) undoped/'/2GaAs layer 3:
1000 [people] (3) For n-type A 1o, 3Ga, 2A s carrier supply N4 Thickness: 100 (people) Donor concentration: I x 10” (cm-3) Donor impurity: Silicon (Si) (4) Undoped A et al. 3 Gao, 7 A s i
i 5) Thickness: 60 [people] (5) Undoped GaAs channel N6 thickness: 200 (people) (6) Undoped A 12 g, 3 Ga,, 7
Thickness of As layer 7: 1500 (person) (7) Thickness of undoped GaAs layer 8:, 5.O
OC person] (8) Undoped A-1a, 5 G a,,, A
Thickness for s layer 9: 60 [person] (9) N-type A et al., s GarIA S Thickness for carrier supply layer 10: 400C person] Donor concentration: lX10 (cm) Donor impurity:
Silicon (Si) aLIln type GaAs1ill thickness: 500 (
] Donor concentration: I x 10''(cm') Donor impurity: Silicon (Si) The manufacturing process of the nonvolatile semiconductor memory device of this example will be described below.

Each of the semiconductor layers described above is sequentially epitaxially grown on a semi-insulating GaAs substrate 1 by a molecular beam epitaxial growth (MBE) method, an MOCVD method, or the like. Here, the undoped Ga p, s that is epitaxially grown first
Layer 2 is intended to improve the crystal properties of the subsequently formed epitaxially grown layer, but it is not necessarily necessary and an ApGaAs layer may be grown to a similar thickness instead.

After forming the n-type GaAs layer 11, for example, AuG is deposited on it.
The source electrode 13 and the drain electrode 14 are formed of an ohmic metal such as e/Au, and then heat-treated to form an undoped G.
A source region 17 and a drain region 18 are formed to be ohmically connected to the aAs channel N5.

Next, the n-type Ga between the source electrode 13 and the drain electrode 14 is
The As layer 11 is removed by, for example, reactive ion etching to form an opening 19, and the n-type G in this opening 19 is removed.
The thickness of the aAs layer is set to about 50 layers.

Therefore, in the opening 19, the layer from the surface of the n-type GaAs layer 11 to the heterojunction formed by the undoped A II Ga As N 9 and the undoped GaAs layer 8 is thin, and the surface depletion spreading from the surface of the n-type GaAs layer is small. The layer does not form a two-dimensional electron gas layer at the heterojunction interface. However, at this thickness, the surface depletion layer is separated from the undoped GaAs layer 6 and -7' A e Ga As
It does not spread to the heterojunction interface due to N 5 , and a two-dimensional electron gas layer 16 is formed at this heterojunction interface.

Next, the gate electrode formation region of the opening 19 of the n-type GaAs 11 is removed by reactive ion etching, etc.
The type AβGaAs layer 10 is exposed.

This allows n-type AI! , the surface depletion layer spreads from the surface of the GaAs JW10, and the undoped G in the gate electrode formation region
The two-dimensional electron gas layer at the heterojunction interface of the aAs layer 6 is eliminated.

Next is n type/'j? For example, Aj in the exposed part of the GaAs layer IO
! A Schottky gate electrode 12 is formed. The formed gate electrode 12, source electrode 13, and drain electrode 14 are provided at different heights with an opening 19 between them, and under the gate electrode 12, an undoped GaAs layer 6 and an opening 19 are provided between them. A two-dimensional electron gas layer is not formed in both of the undoped GaAs layers 8, and a two-dimensional electron gas layer is formed only in the undoped GaAs layer 6 under the opening 19, and under the source electrode 13 and the drain electrode 14. A two-dimensional electron gas layer will be formed in both undoped GaAs layers.

The nonvolatile semiconductor memory device of this embodiment formed as described above changes between a written state and an unwritten state by applying a voltage to the gate electrode 12.

FIG. 3 is a diagram showing the end of the conduction band below the gate electrode 12. FIG. FIG. 1 shows an unwritten state, and the conduction band edge of the portion below the gate electrode 12 at this time is shown in FIG. 3 (al). In the figure, Ef represents Fermi energy, and the undoped GaAs channel layer 6 /'lGaAs layer 5 and undoped GaA
Two hetero interfaces between the s-layer 8 and the undoped GaAs layer 9 are in a state where no two-dimensional electron gas layer is formed. Therefore, there is no movement of two-dimensional electron gas serving as carriers between the source region 17 and the drain region 18, and the region is in a non-conductive state.

In this state, the gate electrode 12 has a thickness of 0.5 to 2 [■].
When a voltage v9 of about 100% is applied, the write state changes to the state shown in FIG. 3(b). At this time, two-dimensional electron gas is induced at each of the two hetero interfaces under the gate electrode 12, and the two-dimensional electron gas layer 16' formed in the undoped GaAs channel layer 6 is connected to the source electrode 13 and the drain electrode 12.
4 is connected to the two-dimensional electron gas layer 16 below, and the source electrode 1
3 and the drain electrode 14 become electrically conductive. Furthermore, a two-dimensional electron gas layer 15 formed on the undoped GaAs layer 8
' is not connected to the two-dimensional electron gas layer 15 in the source region 17 and drain region 18.

Here, even if the voltage application to the gate electrode 12 is stopped, the two-dimensional electron gas in the two-dimensional electron gas layer 15' will be absorbed by the barrier of the undoped ApGaAs layer 9 at the hetero interface, the potential barrier between the gate and source, and between the gate and drain. Therefore, it is not diffused to the source or drain, and the state shown in FIG. 3 (bl) is maintained.

The presence of this two-dimensional electron gas 1'1i15' prevents the surface depletion layer from expanding and the two-dimensional electron gas layer 16' does not disappear, so that the conductive state is maintained. In this state after writing, two two-dimensional electron gases 1i15',
Between 16' and 16' is undoped ApGaA with low electrical conductivity.
Because of the s-layer, the electrons of the two-dimensional electron gas N15' do not move to the two-dimensional electron gas layer 16' over the potential barrier of this layer, resulting in a stable state.

A two-dimensional electron gas layer 15' is formed at the hetero-interface of the undoped GaAs layer 8 below the gate electrode 12, and erasing returns the state where electrons are accumulated to the unwritten state shown in FIG. 3(a). For example, -1 with the opposite polarity when writing to 12.
This is done by applying a voltage of about ~5 [V].

In this example, the undoped GaAs layer 6 and the n
between the type Al1GaAs layers 4 and the undoped GaAs layer 8
and the n-type AlGaAs layer 10, undoped AJGaA
Although the structure includes the s-layers 5 and 9, this is to prevent the mobility of two-dimensional electrons from decreasing due to impurity scattering by donors, and is not necessarily necessary.

As explained above, according to this embodiment, two two-dimensional electron gas layers 15' are formed during writing.

Since it has an undoped AItGaAs layer between 16' and 16', two 2'
The two-dimensional electron gas layers 15' and 16' are completely separated, and the electrons stored in the two-dimensional electron gas layer 15' do not flow, allowing a floating state to be maintained, resulting in a stable storage operation.

FIG. 2 is a sectional view for explaining another embodiment of the present invention.

In the figure, the same parts as in FIG. 1 are designated by the same reference numerals.

In this example, the difference from FIG. 1 is that n-type GaA
The s-layer 11' is formed thin and does not have the opening 19 in the embodiment shown in FIG. 1, so that etching removal for forming this portion is not necessary.

N-type GaAsjill' is formed by epitaxial growth to a thickness of about 50A, and an ohmic electrode 13.
Do 14. The gate electrode formation region of the n-type GaAs layer 11' is removed by etching to expose the n-type AJGaAs carrier supply N10, and the gate electrode 12 is formed in that portion.

However, in this embodiment, compared to the embodiment shown in FIG.
Since it is thin, the ohmic resistance is high. Therefore, in this respect, the embodiment of FIG. 1 is preferable.

〔effect〕

As described above, according to the present invention, in the write hold state, the fourth semiconductor layer is formed with a two-dimensional electron gas layer that accumulates electrons, and the two-dimensional electron gas layer is formed,
By having an undoped third semiconductor layer having a smaller electron affinity than the second and fourth semiconductor layers between the second semiconductor layer and the second semiconductor layer that brings the two ohmically connected electrodes into a conductive state, the fourth The two-dimensional electron gas layer formed in the semiconductor layer and the two-dimensional electron gas layer formed in the second semiconductor layer can be electrically completely separated, and the electrons in the two-dimensional electron gas layer of the fourth semiconductor layer A non-volatile semiconductor memory device with stable operation without any decrease in the amount of noise can be obtained.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view for explaining a non-volatile semiconductor memory device according to one embodiment of the present invention, FIG. 2 is a cross-sectional view for explaining a non-volatile semiconductor memory device according to another embodiment of the present invention, and FIG. 3
The figure shows the conduction band edge under the gate electrode of a non-volatile semiconductor memory device according to an embodiment of the present invention, and FIG. FIG. In the figure, 1 is a semi-insulating Qa, As substrate, 2 is an undoped G
aAs layer, 3 is an undoped A11GaAs layer. 4 is an n-type A3GaAs layer (first semiconductor N), 5 is an undoped A (lGaAsN), 6 is an undoped GaAs1
(second semiconductor N), 7 is an undoped AlGaAs layer (
8 is an undoped GaAs layer (fourth semiconductor M), 9 is an undoped AAGaASI"J, 10
11.11' is an n-type CaAs layer, 12 is a gate electrode, 13 and 14 are a source electrode and a drain electrode, 15.
15', 16, 16' are two-dimensional electron gas layers, 17 and 18
1 is a source region and a drain region, and 19 is an opening. Figure 1 Figure 2 Figure 3 (b)

Claims (1)

[Claims] First and second semiconductor layers, which serve as a first carrier supply layer and a channel layer, are formed in order on a substrate to form a heterojunction, and an undoped semiconductor layer having a lower electron affinity than the second semiconductor layer a fourth semiconductor layer having a higher electron affinity than the third semiconductor layer; a fifth semiconductor layer serving as a second carrier supply layer; and a semiconductor layer disposed on the fifth semiconductor layer. A non-volatile semiconductor memory comprising: a gate electrode provided therein; and two electrodes which are arranged to face each other with the gate electrode interposed therebetween and are each ohmically connected to the second semiconductor layer. Device.