JPS6176505U - - Google Patents
Info
- Publication number
- JPS6176505U JPS6176505U JP16051984U JP16051984U JPS6176505U JP S6176505 U JPS6176505 U JP S6176505U JP 16051984 U JP16051984 U JP 16051984U JP 16051984 U JP16051984 U JP 16051984U JP S6176505 U JPS6176505 U JP S6176505U
- Authority
- JP
- Japan
- Prior art keywords
- muting
- transistor
- time
- base
- control transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
Description
図示した回路は、本考案のミユーテイング回路
の一実施例である。
主な図番の説明、１…磁気ヘツド、２…前置増
幅回路、４…主増幅回路、６…ミユーテイング用
トランジスター、７…信号路、８…第１制御トラ
ンジスター、１０…第２制御トランジスター、１
２…ミユーテイングスイツチ、１４…第１時定数
回路、１７…第２時定数回路。
The illustrated circuit is one embodiment of the muting circuit of the present invention. Explanation of main figure numbers, 1... Magnetic head, 2... Preamplifier circuit, 4... Main amplifier circuit, 6... Muting transistor, 7... Signal path, 8... First control transistor, 10... Second control transistor, 1
2... Muting switch, 14 ... First time constant circuit, 17 ... Second time constant circuit.
Claims (1)
されているミユーテイング用トランジスターと、
該ミユーテイング用トランジスターのベースと電
源との間にコレクタ・エミツタ間が接続されてい
る第１制御トランジスターと、該第１制御トラン
ジスターの動作を制御するべくベースと接地間に
コレクタ・エミツタ間が接続されている第２制御
トランジスターと、ミユーテイング動作時開閉さ
れるミユーテイングスイツチと、該ミユーテイン
グスイツチが閉成状態より開放されたとき前記第
２制御トランジスターのベースに所定時間バイア
ス電流を供給する第１時定数回路と、前記ミユー
テイングスイツチが開放状態より閉成されたとき
前記第１制御トランジスターのベースに所定時間
バイアス電流を流す第２時定数回路とより成り、
前記ミユーテイングスイツチの開閉動作時前記第
１時定数回路及び第２時定数回路により設定され
る所定時間前記ミユーテイング用トランジスター
を導通状態にせしめるようにしたことを特徴とす
るテープレコーダーのミユーテイング回路。 a muting transistor whose collector and emitter are connected between the signal path and ground;
a first control transistor having its collector and emitter connected between the base and the power supply of the muting transistor; and a collector and emitter connected between the base and ground to control the operation of the first control transistor. a second control transistor which is opened and closed during a muting operation; and a first time supplying a bias current to the base of the second control transistor for a predetermined period of time when the muting switch is opened from a closed state. comprising a constant circuit and a second time constant circuit that causes a bias current to flow through the base of the first control transistor for a predetermined time when the muting switch is closed from an open state;
A muting circuit for a tape recorder, characterized in that the mutating transistor is made conductive for a predetermined period of time set by the first time constant circuit and the second time constant circuit when the mutating switch is opened and closed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16051984U JPS6176505U (en) | 1984-10-24 | 1984-10-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16051984U JPS6176505U (en) | 1984-10-24 | 1984-10-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6176505U true JPS6176505U (en) | 1986-05-23 |
Family
ID=30718443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16051984U Pending JPS6176505U (en) | 1984-10-24 | 1984-10-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6176505U (en) |
-
1984
- 1984-10-24 JP JP16051984U patent/JPS6176505U/ja active Pending
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