JPS6175936A - Ram monitor device - Google Patents

Abstract

PURPOSE:To attain debugging at an optional time point by securing the synchronism with execution of a normal program and minitoring and displaying the memory contents with optional timing. CONSTITUTION:A computer system 1 contains a copying RAM3 which holds the contents equal to those of a RAM10 with synchronism. This RAM3 has the capacity corresponding to the address of the RAM10, and the same address is allocated to the RAM3. A CPU12 can have simultaneous access to those addresses. While a controller 5 can have access to the RAM3. An address setting device 7 sets the address of a memory to be monitored. In such constitution, the controller 5 reads the contents of the RAM3 for the address set by the input of an event signal and delivers said contents to a display device 9. Here the contents of the address of the memory to be monitored are displayed in real time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to eight RAM monitors used for depacking programs of a computer system.

[Conventional technology]

A conventional method for depacking a program in a KIN system is to incorporate test instructions for outputting the contents of a register or a predetermined address into some steps of the program.

However, with this method, test instructions for depacking must be inserted one by one, which is a complicated operation.

In particular, in computer systems for control and computer systems for measurement that handle events that vary over time, temporal consistency is maintained in relation to execution by regular programs for test instructions for depacking. The disadvantage is that bugs caused by time factors cannot be accurately depacked. Therefore, in a computer system that collects time-varying events, it is desirable to monitor the contents of the storage device in real time while the computer is in its normal operating state, without stopping the computer.

In order to guarantee such simultaneity, the value of the address register of the computer is monitored, and when this value reaches a predetermined set address value, the data appearing on the data bus is detected. Devices are known that monitor the contents of an address when the address is accessed.

(Patent application 1976-107627) L/Kashi, Depack,
Timings that can be monitored include when the CPU accesses the predetermined address mentioned above, when a certain condition of a physical quantity that fluctuates over time is reached, when a certain period of time has elapsed, and when the CPU accesses the predetermined address.
A request is made when U executes a supporting step stored at a predetermined address.

Conventional monitoring devices use arbitrary timing signals to
It is not possible to monitor the contents of memory at that time in real time.

[Problem to be solved by the invention]

The present invention has been made in order to improve these conventional drawbacks, and its purpose is to monitor and display the contents of memory at any timing while maintaining simultaneity with the execution of regular programs. shall be.

[Means for solving problems]

FIG. 1 is a block diagram showing the concept of the first invention.

The first invention is connected in parallel to a random access memory 10 of a computer system 1 to an address bus 13, a data bus 14, and a control bus 15 of the computer system, and stores addresses of at least a portion of the random access memory 10. Read and write simultaneously in parallel with memory,
Setting the address to be monitored in the copying random access memory 3 and the random access memory 10, which always hold a value equal to the content of the address and are connected to the computer system 1 and independently accessible from the control device 5. An event signal giving the timing to be monitored is input to the address register 7, and when the signal is input, the data in the address area corresponding to the address set by the address setting device 7 is transferred to the random access memory for copying. This RAM monitor device is comprised of a control device 5 that reads data from the computer 3, and a display device 9 that receives signals from the control device 5 and displays the monitored data.

Hereinafter, random access memory will be simply referred to as RAM. A feature of the present invention is that the copying RAM holds the same contents as the contents of the RAM 10 of the computer system 1 at the same time.
3.

The capacity of this RAM 3 for copying does not need to be equal to the capacity of RAM 10, but at least
It is necessary to have a capacity corresponding to the address of M10 and to be allocated an address so that it can be accessed by the same address signal as that address. That is, CPU12
When viewed from above, the RAM 10 and the copying RAM 3 are in a parallel relationship and can be accessed at the same time. On the other hand, the copying RAM 3 can also be accessed from the control device 5.
It is connected to the. The address setting device 7 is used to set the address of the memory to be monitored. For example, the start address and end address to be monitored can be set.
It can be configured with a keyboard or the like that can set multiple specific discrete addresses. In addition, display IV19 is for displaying the contents of the monitored address, and is used as a normal output device,
For example, a CRT, a printer device, etc. can be used. The control device 5 can generally be configured using a computer, a digital circuit, or the like.

The control device 5 reads and outputs the contents of the copying RAM 3 at the address set by inputting the event signal to the display device 9.

With this configuration, when an event signal is input,
The contents of the memory address to be monitored at that time are displayed [
29 in real time.

However, if there are many addresses to monitor, 111
The problem is the time it takes for the No. 11 device 5 to read data from the copying RAM 3 and display it on the display device 9. That is, if the above-mentioned time is long, the copying RAM 3 is rewritten and simultaneity with the event signal is not guaranteed.

Therefore, the second invention is configured to solve this problem. FIG. 2 is a block diagram showing the concept of the second invention.

The second invention is connected to a random access memory 10 of a computer system 1 in parallel and parallel to an address bus 13, a data bus 14, and a control bus 15 of the computer system 1, and from a control device 5 to the computer system 1. A random access memory for copying 31 and a random access memory for monitoring 32 connected to the system 1 so as to be independently accessible, an address setting device 7 for setting an address to be monitored in the random access memory 10, and a timing to be monitored. an event signal input section 51 that inputs an event signal that gives an address; The monitor section 52 reads the contents of the memory corresponding to the address set by the setting device 7, and after the reading is completed, outputs a signal to cancel the prohibition of access to the random access memory 32 for monitoring, and a control device 5 having a data restoration control unit 53 that sequentially transfers the contents of the random access memory 31 to the monitoring random access memory 32; a display device 9 that displays the read contents of the memory;
This is a RAM monitor device consisting of:

In the second invention, the RAM 31 for copying and the RAM 32 for monitoring
Two are installed in parallel. The control device 5 also includes an event signal input section 51, a monitor section 52, and a control section 53. When an event signal is input, the monitor unit 52
disconnects the monitor RAM 32 from the computer system 1 and prohibits data input. Thereafter, the address set by the address setting device 7 is accessed and the contents of the monitor RAM 32 are read.

In parallel with this read operation, the copy RAM 31 has the same contents as the RAM 10 of the computer system 1 rewritten in accordance with the operation of the CPU 2. After the monitor unit 52 completes data reading, the data restoration control unit 53
Connect AM32 to Keihan Machine 1, RAM10, RA for copying
By parallel connection of M31 and monitor RAM32, CPU
The data can be accessed from RAM12, and data can be tracked with respect to RAM10. However, while the monitor unit 52 is inputting data from the monitor RAM 32, the RAM 10
And the contents of the copying RAM 31 have changed. Therefore, in order to make the contents of the monitor RAM 32 the same as the RAM 10, the contents of the copy RAM 31 are transferred to the monitor RAM 32. In this way, the monitor RAM 32 retains the same contents as the copy RAM 31, and therefore the RAM 10
The same content is retained. Further, the display device 9 displays the data read by the monitor unit 52 in a desired format. The present invention consists of the above configuration and operation.

Embodiment 1 FIG. 3 shows a RAM according to a specific embodiment of the second invention.
2 is a block diagram showing the configuration of a monitor device. The copy RAM 31 and the monitor RAM 32 are dual-port RAMs, and are connected to the address bus 13, data bus 14, and control bus 15 of the machine system 1, respectively.

On the other hand, the B boat of each RAM31.32 is the address bus 5.
5, and is connected to the control device 5 by a data bus 56. The control device M5 is composed of a computer system having a CPU 57 and a memory 58. Also, that IIJ
Connected to the ID device 5 are a timer 6 for outputting the time when the event signal 80 is input to the control device 5, a keyboard 7 for setting a monitor address, and a CRT 9 for displaying monitor results.

@Figure 4 shows the CPU 57 used in the device of this embodiment.
3 is a flowchart showing the processing of FIG.

FIG. 5 is a timing chart of input and output signals of the device. The CPU starts execution from step 100, and inputs the address of the RAM to be monitored using the keyboard 7. Next, the process moves to step 102, and if there is no change in the monitor address, the process moves to step 104. Step 1
At step 04, it is determined whether the event signal 80 has been input. If it has been input, the process moves to step 106, and in order to disconnect the monitor RAM 32 from the calculation system 1, the A-boat access prohibition signal 40 is output.

At this time, the monitor RAM 32 retains the contents of the RAM of the computer system at that time. On the other hand, the contents of the copy RAM 31 are continuously rewritten as the computer system operates. Next step 10
8, the contents of the address to be monitored are read from the monitor RAM 32. Next, the process moves to step 110, and the time at which the event signal is generated is read from the timer 6. In step 112, the level of the access prohibition signal 40 is inverted, the monitor RAM 32 is connected to the computer system 1, and the operation in conjunction with the computer system 1 is performed.

Next, in step 114, data is transferred to restore the contents of the monitor RAM 32 to the contents of the copy RAM 31. It outputs an enable signal 41 that also enables reading from the B boat of the copying RAM 31, and
By outputting the write signal 42 to the 'AM 32, the contents of the copy RAM 31 are transferred to the monitor RAM 32. The data strobe signal 45 and address strobe signal 46 output from the computer system 1 are used for the generation timing of various control signals output from the control m+ device 5, respectively.
At the timing of writing to M31.32,
Transfer from RAM 31 to RAM 32 is prohibited to prevent access conflicts. Next, proceed to step 116,
Output the converted data. The output diagram at this time is shown in FIG. In this manner, the second invention device can display the contents of the memory of the computer system while maintaining simultaneity. Although only the embodiment of the second invention has been described above, the first invention uses only a RAM for copying. Therefore, the embodiment of the first invention can be easily understood from the embodiment of the second invention.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the concept of the first invention. FIG. 2 is a block diagram showing the concept of the second invention. FIG. 3 is a block diagram showing the configuration of a RAM monitor device according to a specific embodiment of the second invention. FIG. 4 is a flowchart showing the processing of the CPU used in the device of the same embodiment. FIG. 5 is a timing chart showing the operation of the device of the embodiment. FIG. 6 is an output diagram of the apparatus of the embodiment. 13...Address bus 14...Data bus 15
...Control bus 80...Event signal

Claims (2)

[Claims] (1) Connected to the address bus, data bus, and control bus of the computer system in parallel with the random access memory of the computer system, and read/write simultaneously in parallel with the memory of at least a part of the addresses of the random access memory. a random access memory for copying, which always holds a value equal to the content of the address and is connected to the computer system so that it can be accessed independently from the control device; and an address setting for setting an address to be monitored in the random access memory. a control device that inputs an event signal that gives a timing to be monitored, and when the signal is input, reads data in an address area corresponding to the address set by the address setting device from the random access memory for copying; A RAM monitor device comprising: a RAM monitor device; and a display device that receives signals from the control device and displays monitored data. (2) A copy that is connected in parallel to the random access memory of a computer system to the address bus, data bus, and control bus of the computer system, and that is connected to the computer system so that it can be accessed independently from the control device. an address setting device for setting an address to be monitored in the random access memory; an event signal input section for inputting an event signal giving a timing to be monitored; a monitor unit that outputs a signal to the monitor random access memory to prohibit access from the computer system when the input is input, and reads the contents of the memory corresponding to the address set by the address setting device; a data restoration control unit that outputs a signal to the monitor random access memory to release the prohibition of access after completion of the process, and sequentially transfers the contents of the copy random access memory to the monitor random access memory; A RAM monitor device comprising: a control device having: a display device displaying the read contents of the memory.