JPS6174846A - Automatic registering apparatus - Google Patents

Abstract

PURPOSE:To prevent the generation of the color shift of printed matter by preventing the appearance of an error in the rising of a binary signal, by adjusting a threshold level corresponding to the peak value of each register mark signal before the next register mark signal appears. CONSTITUTION:A mark signal MQ is applied to the input terminal SH of a small hold circuit 1 and the + input terminal of a comparator (CMP)2 while the sample hold circuit 1 indivisually holds the peak value of the inputted register mark signal and outputs the hold content thereof to one terminal of the comparator 2 through a voltage dividing resistor 4 corresponding to the order from a selector 3. Flip-flop 6 is set by a binary signal M and a comparator 15 compares the output Q2 corresponding to the count value of a counter 8 with the data ST1 set from CPU17 through PIO18 and, when both of them coincide (Q2=ST1), a coincidence signal EQ1 is outputted. A comparator 16 compares the output Q3 corresponding to the count value of a counter 12 and data ST2 and, when both of them coincide (Q3=ST2), a coincidence signal EQ2 is outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an automatic registration device used in a multicolor rotogravure printing press or the like.

[Prior art and its problems]

When a multi-colored pattern is printed on a printed matter using a rotary printing machine as described above, the pattern is generally constructed by overlapping each color one by one. In this case, each color may be printed twice, or
Alternatively, in order to avoid misregistration such as margins between colors, it is necessary to correctly align the printing positions of each color. Therefore, conventionally, an automatic registration device has been used. This involves printing marks for each color called register marks at the same time as the image at a predetermined position on the printed material (for example, the edge of μ paper), detecting this with a scanner head during printing, and automatically adjusting the misalignment of each color. There is.

FIG. 7 of the accompanying drawings is an explanatory diagram of the register mark. Identical patterns are arranged on the printing unit 101 at regular intervals (every 1 rib) and are advanced in the direction of arrow a. Register marks 103 for each color are printed on the edge of the printed matter 101 at the same time as the pattern, and these are turned around every ribinot. During printing, such a register mark 10B is detected as an electrical signal by a scanner head, and compared and binarized at a predetermined threshold level and digitally processed.

FIGS. 8 and 9 are waveform diagrams illustrating comparative binarization of register mark signal sequences. The detected register mark signal string is K as shown by the solid line in the figure, and each register mark signal forming the signal string appears at a constant cycle corresponding to each color. This register mark signal is converted into a z-value by comparison at the slave run blind level shown by the solid line in the figure, and then converted into a binary signal (de-metal signal) as shown by the solid line in the figure.
or can be obtained.

However, as is clear from FIGS. 8 and 9, the peak value and signal width of each register mark signal are different for each color. Therefore, as shown by the broken line in Figure @8, when the Thretsnjord level becomes f, the rising and falling points of the z-valued signal corresponding to each register mark signal change, and the amount of change varies for each color. They end up being different sizes.

Also, when the peak value of the register mark signal sequence changes uniformly as shown by the broken line in FIG. 9, the corresponding 2(lt
The rising and falling points of the I signal change, and the amount of change becomes different for each color. As a result, deviations in the rising and falling edges of the binarized signal result in errors in color matching, resulting in drawbacks such as color shift in printed matter.

[Objective of the invention]

The present invention has been designed to overcome the shortcomings of the prior art, and is designed to solve the problem when the threshold signal level changes, or when the peak value of the register mark signal sequence changes. Another object of the present invention is to provide an automatic registration device that prevents color misregistration or the like from occurring in printed matter.

[Summary of development]

In order to achieve the above object, the present invention adjusts the threshold and level level according to the peak value of each register mark signal before the next register mark signal appears.
The present invention provides an automatic registering device that can be used to prevent a rise isobaric error from appearing in a z-valued signal.

[Embodiments of the invention]

Hereinafter, the present invention will be described in detail based on embodiments with reference to FIGS. 1 to 6 of the accompanying drawings. First, before explaining a specific embodiment, the principle of the present invention will be briefly described with reference to FIG. 6. The peak value and signal width of the register mark signal are different for each color. Therefore, the slave and lead levels are switched according to the signal level of each register signal. m6 Figure 1-i This is a waveform diagram when the threshold level is set to 1/2 of the peak value of the register mark signal.If you do this, for example, the level of the register mark signal will change as shown by the broken line in the figure. Also, the threshold and the threshold value change accordingly, and no error appears in the z-valued signal. In addition, in Figure 6, the h thread 7m lead level is 1 of the level of the peak value of the register mark signal.
I have shown the case where it is set to 72, but it is also possible to set it to l/8.278
However, any type of signal may be used as long as it changes according to the signal level of the register mark.

@1 Figure is a circuit diagram of one embodiment of the present invention. Eight types of signals are input from the outside: a gate signal G, a pulse signal C, and a mark signal MQ. The gate signal G is for extracting only the register mark signal from the output signal of the scanning head, the pulse signal C is the output signal of a pulse generator that generates a continuous clock pulse of a desired period, and the mark signal MQ is This is the output signal of the scanning head that detected each register mark.

Mark signal MQ is input terminal 8 of sample hold circuit 1
4 is applied to the input terminal of comparator (CMP) 2. The sample hold circuit 1 individually holds the peak values of the input register mark signals, and outputs the held contents to one terminal of the comparator 2 via the voltage dividing resistor 4 in response to a command from the selector 3.

At this time, if the voltage dividing ratio of the voltage dividing resistor 4 is set to 1=1,
This means that the comparator 2 is supplied with a voltage of 1/2 of the peak value of the register mark signal.

The z-valued signal M binarized by the comparator 2 is sent to the clock terminal C of the flip-flop (F/F) 6 via the OR gate 5.
It is also applied to the reset terminal R of the color/input (CTI) 8 via the OR gate 7.

The gate signal G is applied to the clock terminal CK of the counter 8 via the AND gate 9, and the gate signal G inverted by the inverter 10 is applied to the reset terminal R of the counter 8 via the OR gate 7. It is applied to the reset terminal of the color/receiver (Cr2) 12 through the input terminal 12, and directly to the counter (CTa)ll'l. Further, a pulse signal (a pulse signal is given to the clock terminal CK of the counter 12 via the 4AND gate 14).

The counter 8 is reset by the inverted gate signal 01 applied via the OR gate 7 or the binary signal M or the output (match signal) BQI of the comparator 15, and when the gate signal G is 1 (
When G is U), pulse signal C is counted up and (
An output Q2 corresponding to the count value is given to the A terminal of the comparator 15. The counter 12 is the output Q1 of the flip tab 6.
When G is 1, the pulse signal C is counted up, and when the inverted gate signal G is 1, or the match signal EQ2 output from the comparator 16 is reset to 1.

The flip 70 knob 6 is set by the z-valued signal M and reset by the output (coincidence signal) EQ2 of the comparator 16. The counter 18 is reset by the inverted gate signal G, counts up the output EQ2 of the comparator 16, and provides an output Q4 corresponding to the count value to the selector (SL) 8.

C) STI output from 'U17 and PIOI8.

8T2 is digital data that has been compared to t in order to make it correspond to the actual position on the wear since the pulse signal C is distorted in the time domain.
．． 16 to the B terminal.

Therefore, the comparator 15 compares the output Q2 corresponding to the count value of the color/return 8 and the data STI set by the CPU 17 via the PIOI 8, and when they match (
'Q2=STl), a match signal gQ1 is output. Further, the comparator 16 is 2' of the counter 1z.

Output QB according to the count value and data ST2 are compared, and when they match (QB=ST2), a match signal BQ2 is generated.
Output.

Figure 2 is a detailed circuit diagram of the sample and hold circuit shown in Figure 1. 1 sample hold circuit and 9 corresponding register mark signals of 7 colors, and 7
It has three sample holders 21-27. Analog switches 81 to 1.41-4 on the input and output sides
7 are respectively switched by the output signal of the selector 8, and when the analog switches 31 to 87 on the input side are open, the peak value of the register mark signal included in the mark signal MQK is stored in the sample and hold units 21 to 27 for each color. with subsequent analog switches 81-87
is held by the closing of the analog switch 41 on the output side.
.about.47 is closed, the held contents are provided to the comparator 2 as the threshold voltage level via the voltage dividing resistor.

FIG. 8 is a waveform diagram showing the relationship between gate signal G and mark signal MQ. When the gate signal G is 1, the register mark signals appear at approximately constant intervals.

Assuming that the intervals between the register marks of seven colors on the paper are 20, the time between signals is also 20 short beats long. Gate signal G is applied to counters 8, 12 . This is a condition for resetting lf3 and a condition for counting up the pulse signal C in the small counter 8. Therefore, when the gate signal G is 1, only the register mark signal is extracted from the mark signal MQ. That's it.

4 and 5 are time charts for explaining the operation of the embodiment shown in FIGS. 1 and 2. FIG. 4 shows a case where all register mark signals are detected, and FIG. indicates a case where some register mark signals are not detected.

First, the operation will be explained with reference to Figure @4. In addition, in the interval between songs shown in FIG. 4, the gate signal G is always 1, and the pulse signal C is always applied. Further, when printing the first color picture, it is assumed that the interval of the register mark signal is stored in the CPU 17, and the peak value of the register mark signal of each color is individually held in the sample hold circuit 1.

When the mark signal MQ rises at time t1 and its level exceeds the threshold level, the output (binarized signal) FiO of the comparator 2 goes from 1 to 1, and the output Q1 of the 71J block flop 6 goes from 0 to IK. Therefore, the AND gate 14 is opened and the pulse signal C is sent to the clock terminal CKK of the counter 12.
It is input (OK2).

In response to this K, the counter 12 starts counting the pulse signal c6 and provides an output signal Q8 (data corresponding to the elapsed time from time 1) to the comparator 16.

At this time, the input (B) K of the comparator 16 is PI
Since pre-stored data 8T2 (data corresponding to the time from the appearance of a certain register mark signal until the threshold level is changed) is given from O, when these match (QB=ST2
) Match signals F, Q2 are output. Match signal gQ2
When is output, the counter 12 is reset and counting up of the pulse signal C is stopped. flip 7 at the same time
0 cup 6 is also reset, and its output Ql changes from 1 to OK.

Further, since the match signal EQ2 is also input to the counter 1BK, the counter 18 counts it and the count value becomes 1), and its output Q4 (count value 1) is given to the selector 8. Selector 8 is the output Q of cuff/li 13
4, the corresponding analog switch on the output side of the sample-and-hold circuit 1 is switched, and thereby the threshold level applied to the comparator 2 is switched to a level corresponding to the peak value of the register mark signal.

After the predetermined time has elapsed, time 1 is returned. When the mark signal MQ rises, the output of the comparator 2 becomes 1, and the output Q1 of the flip-flop 6 becomes IK. After that, the same operation as above is returned.

In the above example, the output of the comparator 16 (coincidence signal) g
The coincidence signal EQ2 is outputted so that the time point at which the signal Q,2 is outputted is approximately in the middle of the time point at which the mark signal MQ rises, but is not limited to this. 1, and the threshold level may be changed at any point in time.

Next, due to poor printing of the register mark, etc., the mark signal M
The operation when the rising edge of Q does not appear will be explained with reference to the time chart in Figure @5. When the mark signal rises at time t, the binary signal M becomes 0 (IK), so the output Q1 of the flip-flop 6 becomes IK, and the counter L2
The count-up of the pulse signal C is started (
OK2). At the same time, the binary signal M/OR is applied to the reset terminal of the counter 8 via the gate 7, so (
R1), the counter 8 is reset and starts counting up the pulse signal C, and provides its output signal Q2 (count value) to the comparator 15.

If the mark signal MQ does not rise due to a printing defect or the like at time t4, the binary signal MFil does not rise.

Therefore, the output Ql+-11 of the 711 block flop 6 will not be obtained as it is, but the comparator 15 receives the output Q, 2 of the counter 8 (count value corresponding to the elapsed time from time t) and the data 5TI from the PIO 18. (data corresponding to the interval between two register marks) is given, so at time t4, Q2=8Tl and the coincidence signal EQI is output (becomes 1). Match signal EQI
resets the counter 8 and also resets the 7 lip-flop 6.
Set f. When the flip 70 knob 6 is set, its output Q1 becomes 0 or IK, and the counter 12 can restart counting up the pulse signal C.

When Q8=ST2 after a predetermined time has elapsed from time t, the comparator 16 outputs a match signal FiQ2, and the counter 18 counts up. Since the count data (count value 2) from this counter 18 is given to the selector 8, the sample and hold circuit 1 is switched to select the thread corresponding to the next register mark signal.
The W level is set.

Note that the sample and hold circuit, selector, etc. may be configured by a microprocessor or the like.

〔Effect of the invention〕

As described above, in the present invention, data corresponding to the peak value of each register mark signal is held in the sample and hold circuit,
Based on this, the next register mark signal appears Mf
I pressed you to adjust the lK thread/jord level, so
Even when the peak value of the register mark signal fluctuates due to a change in the degree of printing A for each color, it is possible to obtain an automatic registration device that prevents color marks from occurring on printed matter.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is F, 1
Detailed circuit diagram of the sample and hold circuit shown in Figure,v,3
The figure is a waveform diagram explaining the relationship between the gate signal and mark signal.
4 and 5 are time charts explaining the operation of the embodiment shown in FIGS. 1 and 2, FIG. 6 is a waveform diagram explaining the present invention in detail, and FIG. 7 is an explanatory diagram of register marks. According to FIG. 8, FIG. 9 is a modified diagram for explaining the problems of the Jubeishai technique. 1...Sample and hold circuit 2, 15.16...Comparator 3...Selector 4...Voltage dividing resistor 5.7.11...0f-L gate 6...7 Linopfronop 8.12. 13... Color/Re9.14... AND gate 10... Inverter 17... CPU 18... PIO101
°゛・Printed material 102...Picture 103...Register mark patent applicant Nippon Regulator Co., Ltd. Anshaike 1
Name '' Figure 2 Figure 3 Figure 4 Q4 1
2.8” Figure 5 Crt, +
2 3 H Fig. 6 Register mark signal Fig. 7

Claims (2)

[Claims] (1) Extract register marks arranged and printed at regular intervals on printed matter as a periodic register mark signal sequence,
In an automatic registration device that adjusts a printing position based on a binary signal sequence obtained by comparing and binarizing this register mark signal sequence at a predetermined threshold level, the peak of the register mark signal constituting the register mark signal sequence is determined. sample-and-hold means for holding signals corresponding to respective values; switching means for outputting a switching signal at the same period as the register mark signal string; and changing means for changing the threshold level to a level corresponding to the peak value of the register mark signal that appears next. (2) The sample and hold means includes a sample and hold device that individually holds register mark signals corresponding to register marks of each color, and an analog switch provided for each sample and hold device. Automatic matchmaking device according to scope 1.