JPS6174128U - - Google Patents
Info
- Publication number
- JPS6174128U JPS6174128U JP15945484U JP15945484U JPS6174128U JP S6174128 U JPS6174128 U JP S6174128U JP 15945484 U JP15945484 U JP 15945484U JP 15945484 U JP15945484 U JP 15945484U JP S6174128 U JPS6174128 U JP S6174128U
- Authority
- JP
- Japan
- Prior art keywords
- computer
- various operations
- predetermined time
- counter
- controls various
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案回路の一実施例の回路構成図、
第２図は第１図示のコンピユータの実行する処理
の各実施例のフローチヤートである。
１…コンピユータ、３…カウンタ、４…クロツ
ク信号発生器、５…単安定マルチバイブレータ、
６…インバータ。
FIG. 1 is a circuit configuration diagram of an embodiment of the circuit of the present invention.
FIG. 2 is a flowchart of each embodiment of the processing executed by the computer shown in FIG. 1... Computer, 3... Counter, 4... Clock signal generator, 5... Monostable multivibrator,
6...Inverter.
Claims (1)
においては所定時間間隔内毎にパルスを出力する
コンピユータに設けられ、該パルスによりリセツ
トされ、かつ一定周期で入来するクロツク信号を
計数してその計数値が該所定時間間隔に相当する
値より充分大なる所定値を越えたときリセツト信
号を発生するカウンタよりなり、該コンピユータ
の暴走時に該カウンタが発生するリセツト信号を
該コンピユータに供給してリセツトするリセツト
回路。 (2) 該コンピユータは、テレビジヨン受像機の
各種動作制御を行なう実用新案登録請求の範囲第
１項記載のリセツト回路。[Claims for Utility Model Registration] (1) Provided in a computer that controls various operations of equipment and outputs pulses at predetermined time intervals under normal operating conditions; a counter that counts clock signals that occur and generates a reset signal when the counted value exceeds a predetermined value that is sufficiently larger than the value corresponding to the predetermined time interval, and the reset signal that the counter generates when the computer runs out of control. A reset circuit that resets the computer by supplying it to the computer. (2) The reset circuit according to claim 1, wherein the computer controls various operations of a television receiver.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15945484U JPS6174128U (en) | 1984-10-22 | 1984-10-22 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15945484U JPS6174128U (en) | 1984-10-22 | 1984-10-22 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6174128U true JPS6174128U (en) | 1986-05-20 |
Family
ID=30717410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15945484U Pending JPS6174128U (en) | 1984-10-22 | 1984-10-22 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6174128U (en) |
-
1984
- 1984-10-22 JP JP15945484U patent/JPS6174128U/ja active Pending
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