JPS616896A - Method of tripping multilayer circuit board - Google Patents

Method of tripping multilayer circuit board

Info

Publication number
JPS616896A
JPS616896A JP59126677A JP12667784A JPS616896A JP S616896 A JPS616896 A JP S616896A JP 59126677 A JP59126677 A JP 59126677A JP 12667784 A JP12667784 A JP 12667784A JP S616896 A JPS616896 A JP S616896A
Authority
JP
Japan
Prior art keywords
circuit
circuit board
multilayer circuit
multilayer
tripping
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59126677A
Other languages
Japanese (ja)
Inventor
長南 幸三
最上 和親
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP59126677A priority Critical patent/JPS616896A/en
Publication of JPS616896A publication Critical patent/JPS616896A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層プリントコイル等圧用いられる多層回路板
のトリミング方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for trimming a multilayer circuit board in which a multilayer printed coil isostatically used.

〔発明の技術的背景およびその問題点〕フラットモータ
等に用いられる多層プリントコイルはプラスチックフィ
ルム基材の片面あるいは両面に類似形状の回路部を形成
したフレキシブル回路板を接着性を有する絶縁材を介し
て多数枚積層したものである。かNる多層回路板は通常
比較的大きな面積の基材に多数の回路パターンを形成し
た後単位回路ブロックに切断され積層後ルータあるいは
打抜加工等によって所定形状にトリミングされる。
[Technical background of the invention and its problems] Multilayer printed coils used in flat motors etc. are made by connecting a flexible circuit board with circuit parts of similar shape formed on one or both sides of a plastic film base material through an adhesive insulating material. It is made by laminating many sheets. Generally, a multilayer circuit board is formed by forming a large number of circuit patterns on a base material having a relatively large area, and then cutting the board into unit circuit blocks. After lamination, the board is trimmed into a predetermined shape using a router or punching process.

しかしルータ加工は操作が複雑でかつ時間がかかるため
に量産性に欠ける。−1打抜加工は%t ++’lz性
の面で有利であるが、基材の打抜部に大きな衝撃力が加
わるために基材が打抜き方向にダして外観を損なったり
、層間の回路部が接触することによる接続不良、衝撃に
よる回路部の断線および変形が生じ易いといった問題が
あった。
However, router machining is complicated and time-consuming, making it difficult to mass-produce. -1 punching process is advantageous in terms of %t++'lz property, but since a large impact force is applied to the punched part of the base material, the base material may dent in the punching direction, spoiling the appearance, or causing damage between the layers. There have been problems such as poor connection due to contact between the circuit parts and breakage and deformation of the circuit parts due to impact.

〔発明の目的〕[Purpose of the invention]

本発明はか〜る状況に鑑みなされたものであって、上記
の如き欠点のない多層回路板のトリミング方法を提供せ
んとするものである。
The present invention has been made in view of the above situation, and it is an object of the present invention to provide a method for trimming a multilayer circuit board that does not have the above-mentioned drawbacks.

〔発明の開示〕[Disclosure of the invention]

すなわち、本発明の要旨は少なくとも片面に回路を形峻
したフレキシブル回路板を複数枚積層してなる多層回路
板のトリミング方法において、回路形成部と非回路部の
境界にそれぞれ同一パターンを有する細巾状の非41t
fj帯を形成したフレキシブル回路板を積層接着すると
とも((、前記非導通帯部を打抜き加工することを特徴
とする多層回路板のトリミング方法にある。
That is, the gist of the present invention is to provide a method for trimming a multilayer circuit board formed by laminating a plurality of flexible circuit boards each having a circuit formed on at least one side, in which a thin strip having the same pattern at the boundary between a circuit forming part and a non-circuit part is provided. non-41t
A method for trimming a multilayer circuit board is characterized in that flexible circuit boards on which fj bands are formed are laminated and bonded, and the non-conductive band portions are punched out.

本発明−おいて回路部とは所定形状の回路形成部外郭線
で囲まねた部分を指す。また非回路部とは前記回路部以
外の部分を指すものとする。
In the present invention, the circuit portion refers to a portion surrounded by an outline of a circuit forming portion having a predetermined shape. Further, the non-circuit portion refers to a portion other than the circuit portion.

非導通帯の形成方法としてはフレキシブル回路板の回路
形成時に回路部と非回路部の境界に沿って50〜500
μm程俄の細巾状に金属をエツチングにより除去する方
法(エツチング法)あるいはあらかじめ非導通帯を形成
すべく作られたフォトマスク圧よって前記非導通帯をレ
ジスト像として残し回路部と非回路部をメッキすること
により非導通帯を形成する方法(メッキ法)などがある
。非導通帯の巾は通常50〜500μmが採用されるが
好ましくは80〜200μが適している。この値以下で
は打抜時の位置合せが難かしく、それ以上では打抜時ダ
レが生じ易くなる。
The method for forming the non-conducting band is as follows: 50 to 500 strips are formed along the boundary between the circuit part and the non-circuit part when forming the circuit on the flexible circuit board.
The non-conducting band is left as a resist image by a method of removing the metal in a narrow width of approximately μm (etching method) or by using a photomask pressure created in advance to form the non-conducting band, and the circuit area and the non-circuit area are removed. There is a method of forming a non-conductive zone by plating (plating method). The width of the non-conducting band is usually 50 to 500 μm, preferably 80 to 200 μm. Below this value, alignment during punching is difficult, and above this value, sagging during punching is likely to occur.

以下本発明の実施の態様を実施例に基すき説明するが本
発明は以下の実施例に限定されるものではない。
The embodiments of the present invention will be described below based on Examples, but the present invention is not limited to the following Examples.

実施例 厚さが35μmのポリエステルフィルムの両面に同じ厚
みを有する銅箔をエポキシ系接着剤で貼合せ、両面の銅
箔面にエツチング法により回路部、非回路部および非導
通帯を形成した両面フレキシブル回路板を得た。第1図
はかNる回踏板を示すもので1が回路部、2は非回路部
、3は巾を100μとした非導通帯である。ついで上記
両面フレキシブル回路板を、絶縁性の接着フィルムによ
り10層積層し熱プレス忙より接着した後各層の導通を
スルホールメッキ等にて接続し、これを第2図に示すよ
うに非導通帯3の中心に沿って打抜くことにより基材の
ダレ、層間接続や回路破壊のない多層回路板を得た。
Example: Copper foils having the same thickness were laminated on both sides of a polyester film with a thickness of 35 μm using an epoxy adhesive, and circuit areas, non-circuit areas, and non-conductive bands were formed on both sides of the copper foil surfaces by an etching method. A flexible circuit board was obtained. FIG. 1 shows a turning board, in which 1 is a circuit section, 2 is a non-circuit section, and 3 is a non-conducting band with a width of 100 .mu.m. Next, 10 layers of the double-sided flexible circuit board were laminated using insulating adhesive films and bonded by hot pressing, and the conductivity of each layer was connected by through-hole plating, etc., and this was formed into a non-conductive band 3 as shown in FIG. By punching along the center of the board, we obtained a multilayer circuit board with no sagging of the base material, no interlayer connections, and no circuit damage.

〔発明の効果〕〔Effect of the invention〕

本発明は十述のごとく回路部と非回路部の境界に細巾状
の非4辿帯を設けたフレキシブル回路板を積層し各層の
非導通帯の中心を打抜(よう妊したので各層に形成され
た回路部と非回路部の銅部のエッヂにより高剪断力が基
材に集中し、打抜かれるので基材のダレ、層間接続不良
や回路破壊のない多I鋪回路板が得られる。
As described above, in the present invention, flexible circuit boards each having a narrow non-conducting strip at the boundary between a circuit section and a non-circuit section are laminated, and the center of the non-conducting strip of each layer is punched out. High shear force is concentrated on the base material due to the edges of the copper parts of the formed circuit part and non-circuit part, and punching is performed, resulting in a multi-I circuit board without sagging of the base material, poor interlayer connection, or circuit breakage. .

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の実施例を示し第1図はフレキシブル回路
板の斜視図、第2図は多層回路板の断面図である。 1、回路部    2.非回路部 5 非導通部   4.基材 5、接着剤    61位置決孔 第1図 第2図
The drawings show an embodiment of the present invention, and FIG. 1 is a perspective view of a flexible circuit board, and FIG. 2 is a sectional view of a multilayer circuit board. 1. Circuit section 2. Non-circuit part 5 Non-conducting part 4. Base material 5, adhesive 61 positioning hole Fig. 1 Fig. 2

Claims (1)

【特許請求の範囲】[Claims] 1、少なくとも片面に回路を形成したフレキシブル回路
板を複数枚積層してなる多層回路板のトリミング方法に
おいて、回路形成部と非回路部の境界にそれぞれ同一パ
ターンを有する細巾状の非導通帯を形成したフレキシブ
ル回路板を積層接着するとともに、前記非導通帯部を打
抜き加工することを特徴とする多層回路板のトリミング
方法。
1. In a method for trimming a multilayer circuit board formed by laminating a plurality of flexible circuit boards each having a circuit formed on at least one side, a narrow non-conductive band having the same pattern is provided at the boundary between the circuit forming part and the non-circuit part. A method for trimming a multilayer circuit board, which comprises laminating and bonding the formed flexible circuit boards and punching out the non-conductive band portions.
JP59126677A 1984-06-20 1984-06-20 Method of tripping multilayer circuit board Pending JPS616896A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59126677A JPS616896A (en) 1984-06-20 1984-06-20 Method of tripping multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59126677A JPS616896A (en) 1984-06-20 1984-06-20 Method of tripping multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS616896A true JPS616896A (en) 1986-01-13

Family

ID=14941122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59126677A Pending JPS616896A (en) 1984-06-20 1984-06-20 Method of tripping multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS616896A (en)

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