JPS6168580U

JPS6168580U -

Info

Publication number: JPS6168580U
Application number: JP15132884U
Authority: JP
Priority date: 1984-10-06
Filing date: 1984-10-06
Publication date: 1986-05-10

Description

[Brief explanation of the drawing]

第１図は従来のフレーム記憶装置を示すブロツ
ク図、第２図は、映像信号のサンプリング例を示
す図、第３図は従来のフレーム記憶装置を倍密度
走査テレビジヨンに使用した例を示すブロツク図
、第４図は本考案の実施例を示すブロツク図、第
５図は本考案の具体回路のブロツク図、第６図及
び第７図は演算処理を説明する為の参考図、第８
図は演算部の動作手順を説明するフローチヤート
図、第９図は、液晶デイスプレイ装置のブロツク
図。主要部分の符号の説明、１……アナログ・デイ
ジタル変換部、２……フレームメモリ、３，２７
……コントローラ、４……デイジタル・アナログ
変換部、２７ａ……制御部、２７ｂ……信号生成
部、２８……スイツチ回路、３０……演算制御部
、３３……２Ｈレジスタ、３４……演算部、３５
……１Ｈレジスタ。 FIG. 1 is a block diagram showing a conventional frame storage device, FIG. 2 is a diagram showing an example of sampling a video signal, and FIG. 3 is a block diagram showing an example of using the conventional frame storage device in double-density scanning television. 4 is a block diagram showing an embodiment of the present invention, FIG. 5 is a block diagram of a specific circuit of the present invention, FIGS. 6 and 7 are reference diagrams for explaining arithmetic processing, and FIG.
The figure is a flowchart explaining the operating procedure of the arithmetic section, and FIG. 9 is a block diagram of the liquid crystal display device. Explanation of symbols of main parts, 1...Analog-digital converter, 2...Frame memory, 3, 27
... Controller, 4 ... Digital-to-analog converter, 27a ... Control section, 27b ... Signal generation section, 28 ... Switch circuit, 30 ... Arithmetic control section, 33 ... 2H register, 34 ... Arithmetic section , 35
...1H register.

補正昭６０．２．１８図面の簡単な説明を次のように補正する。明細書第１８頁第４行〜第５行の「第６図及び
第７図は演算処理を説明する為の参考図」を「第
６図及び第７図は演算処理を説明する為の図」と
訂正する。Amendment February 18, 1980 The brief description of the drawing is amended as follows. ``Figures 6 and 7 are reference figures for explaining arithmetic processing'' in lines 4 and 5 of page 18 of the specification are changed to ``Figures 6 and 7 are diagrams for explaining arithmetic processing.'' ” he corrected.

Claims

[Scope of utility model registration request]

A storage means for sequentially storing pixel signal values, a signal generation means for generating a pseudo value of a pseudo pixel from the group of pixel signal values of the storage means, and a switching means for supplying the pixel signal value or the pseudo value. In the frame storage device of the image reproducing device, the signal generating means stores the current pseudo value of a pseudo pixel at a certain position on the screen for each pixel that is vertically vertically or diagonally above and below the pseudo pixel. A frame storage device characterized in that a pseudo value is sequentially generated by a weighted average of each pixel signal value and a previous pseudo value.